DF2117VT20V Renesas Electronics America, DF2117VT20V Datasheet - Page 251

• Manufacturer Part Number: DF2117VT20V
• Description: MCU 16BIT FLASH 3V 160K 144-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2117VT20V

• Core Processor: H8S/2600
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: FIFO, I²C, LPC, SCI, SmartCard
• Peripherals: POR, PWM, WDT
• Number Of I /o: 112
• Program Memory Size: 160KB (160K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-TQFP, 144-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

8.3.6
PWMREG0 to PWMREG5 are 8-bit readable/writable registers used to set the high period (duty)
of the PWM output pulse. The initial value is H'00.
(1)
Directly set the high period of the pulse for PWM output. With PWMREG registers, the duty
cycle of the PWM output pulse is specified as a value from 0/255 to 255/255 with a resolution of
1/255.
When the PWMREG value is m, the high period of the output pulse is calculated as follows:
(2)
Directly set the high period of the pulse for PWM output. With cascade-connected PWMREG
registers, the duty cycle of the PWM output pulse is specified as a value from 0/65535 to
65535/65535.
When the PWMREG value is m, the high period of the output pulse is calculated as follows:
Set the respective high-level pulse periods by using the following register combinations (cascaded
connection): PWMREG1 (higher order) and PWMREG0 (lower order), PWMREG3 (higher order)
and PWMREG2 (lower order), and PWMREG5 (higher order) and PWMREG4 (lower order).
(3)
Specify the basic pulse duty cycle and the number of additional pulses for PWM output. The
higher-order four bits of the PWMREG setting specify the duty cycle of the basic pulse as 0/16 to
15/16 with a resolution of 1/16, and the lower-order four bits specify the number of pulses to be
added within the conversion period comprising the basic pulses.
8-Bit Single Pulse Mode
16-Bit Single Pulse Mode
8-Bit Pulse Division Mode
Output pulse high period = (PWM cycle × m) / 255 (0 ≤ m ≤ 255)
Output pulse high period = (PWM cycle × m) / 65535 (0 ≤ m ≤ 65535)
PWM Duty Setting Registers 0 to 5 (PWMREG0 to PWMREG5)
Rev. 2.00 Sep. 28, 2009 Page 209 of 994
REJ09B0452-0200