DF2117VT20V Renesas Electronics America, DF2117VT20V Datasheet - Page 300

MCU 16BIT FLASH 3V 160K 144-TQFP

DF2117VT20V

Manufacturer Part Number
DF2117VT20V
Description
MCU 16BIT FLASH 3V 160K 144-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2100r
Datasheet

Specifications of DF2117VT20V

Core Processor
H8S/2600
Core Size
16-Bit
Speed
20MHz
Connectivity
FIFO, I²C, LPC, SCI, SmartCard
Peripherals
POR, PWM, WDT
Number Of I /o
112
Program Memory Size
160KB (160K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 16x10b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
144-TQFP, 144-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

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Part Number
Manufacturer
Quantity
Price
Part Number:
DF2117VT20V
Manufacturer:
Renesas
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Part Number:
DF2117VT20V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
10.3.4
The TIER registers control enabling or disabling of interrupt requests for each channel. The TPU
has three TIER registers, one for each channel.
Rev. 2.00 Sep. 28, 2009 Page 258 of 994
REJ09B0452-0200
Bit
7
6
5
4
3
Bit Name
TTGE
TCIEU
TCIEV
TGIED
Timer Interrupt Enable Register (TIER)
Initial
value
0
1
0
0
0
R/W
R/W
R
R/W
R/W
R/W
Description
Enables or disables generation of A/D conversion start
requests by TGRA input capture/compare match.
0: A/D conversion start request generation disabled
1: A/D conversion start request generation enabled
Reserved
This bit is always read as 1 and cannot be modified.
Underflow Interrupt Enable
Enables or disables interrupt requests (TCIU) by the
TCFU flag when the TCFU flag in TSR is set to 1 in
channels 1 and 2. In channel 0, bit 5 is reserved.
0: Interrupt requests (TCIU) by TCFU disabled
1: Interrupt requests (TCIU) by TCFU enabled
Enables or disables interrupt requests (TCIV) by the
TCFV flag when the TCFV flag in TSR is set to 1.
0: Interrupt requests (TCIV) by TCFV disabled
1: Interrupt requests (TCIV) by TCFV enabled
TGR Interrupt Enable D
Enables or disables interrupt requests (TGID) by the
TGFD bit when the TGFD bit in TSR is set to 1 in
channel 0. In channels 1 and 2, bit 3 is reserved. It is
always read as 0 and cannot be modified.
0: Interrupt requests (TGID) by TGFD disabled
1: Interrupt requests (TGID) by TGFD enabled.
A/D Conversion Start Request Enable
Overflow Interrupt Enable

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