DF2117VT20V Renesas Electronics America, DF2117VT20V Datasheet - Page 172
DF2117VT20V
Manufacturer Part Number
DF2117VT20V
Description
MCU 16BIT FLASH 3V 160K 144-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2100r
Datasheet
1.DF2117VT20HV.pdf
(1040 pages)
Specifications of DF2117VT20V
Core Processor
H8S/2600
Core Size
16-Bit
Speed
20MHz
Connectivity
FIFO, I²C, LPC, SCI, SmartCard
Peripherals
POR, PWM, WDT
Number Of I /o
112
Program Memory Size
160KB (160K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 16x10b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
144-TQFP, 144-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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5.8.2
The instructions that disable interrupts are LDC, ANDC, ORC, and XORC. After any of these
instructions are executed, all interrupts including NMI are disabled and the next instruction is
always executed. When the I bit or UI bit is set by one of these instructions, the new value
becomes valid two states after execution of the instruction ends.
5.8.3
Interrupt operation differs between the EEPMOV.B instruction and the EEPMOV.W instruction.
With the EEPMOV.B instruction, an interrupt request including NMI issued during data transfer is
not accepted until data transfer is completed.
With the EEPMOV.W instruction, if an interrupt request is issued during data transfer, interrupt
exception handling starts at a break in the transfer cycles. The PC value saved on the stack in this
case is the address of the next instruction. Therefore, if an interrupt is generated during execution
of an EEPMOV.W instruction, the following coding should be used.
5.8.4
Switching between H8S/2140B Group compatible vector mode and extended vector mode must be
done in a state with no interrupts occurring.
If the EIVS bit in SYSCR3 is changed from 0 to 1 when interrupt input is enabled because the
KIN15 to KIN0 and WUE15 to WUE8 pins are set at low level, a falling edge is detected, thus
causing an interrupt to be generated. The vector mode must be changed when interrupt input is
disabled, that is the KIN15 to KIN0 and WUE15 to WUE8 pins are set at high level.
Rev. 2.00 Sep. 28, 2009 Page 130 of 994
REJ09B0452-0200
L1:
Instructions for Disabling Interrupts
Interrupts during Execution of EEPMOV Instruction
Vector Address Switching
EEPMOV.W
MOV.W
BNE
R4,R4
L1
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