DF2117VT20V Renesas Electronics America, DF2117VT20V Datasheet - Page 461

• Manufacturer Part Number: DF2117VT20V
• Description: MCU 16BIT FLASH 3V 160K 144-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2117VT20V

• Core Processor: H8S/2600
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: FIFO, I²C, LPC, SCI, SmartCard
• Peripherals: POR, PWM, WDT
• Number Of I /o: 112
• Program Memory Size: 160KB (160K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-TQFP, 144-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

15.3.9
BRR is an 8-bit register that adjusts the bit rate. As the SCI performs baud rate generator control
independently for each channel, different bit rates can be set for each channel. Table 15.3 shows
the relationships between the N setting in BRR and bit rate B for normal asynchronous mode and
clocked synchronous mode, and smart card interface mode. The initial value of BRR is H'FF. The
CPU can always read BRR. The CPU can write to BRR only at the initial settings; do not have the
CPU write to BRR in transmission, reception, and simultaneous data transmission and reception.
Table 15.3 Relationships between N Setting in BRR and Bit Rate B
[Legend]
Table 15.4 shows sample N settings in BRR in normal asynchronous mode. Table 15.5 shows the
maximum bit rate settable for each frequency. Table 15.7 and 15.9 show sample N settings in
BRR in clocked synchronous mode and smart card interface mode, respectively. In smart card
interface mode, the number of basic clock cycles S in a 1-bit data transfer time can be selected.
For details, see section 15.7.4, Receive Data Sampling Timing and Reception Margin. Tables 15.6
and 15.8 show the maximum bit rates with external clock input.
Mode
Asynchronous mode
Clocked synchronous mode
Smart card interface mode
SMR Setting
CKS1
0
0
1
1
Bit Rate Register (BRR)
B:
N:
φ:
n and S:
Bit rate (bit/s)
BRR setting for baud rate generator (0 ≤ N ≤ 255)
Operating frequency (MHz)
Determined by the SMR settings shown in the following table
CKS0
0
1
0
1
Bit Rate
B =
B =
B =
n
0
1
2
3
8 × 2
S × 2
64 × 2
φ × 10
2n – 1
2n + 1
φ × 10
φ × 10
2n – 1
× (N + 1)
× (N + 1)
6
× (N + 1)
6
6
SMR Setting
BCP1
0
0
1
1
Rev. 2.00 Sep. 28, 2009 Page 419 of 994
Error
Error (%) = {
⎯
Error (%) =
BCP0
0
1
0
1
{
B × 64 × 2
B × S × 2
φ × 10
2n – 1
2n + 1
REJ09B0452-0200
φ × 10
6
× (N + 1)
× (N + 1)
6
S
32
64
372
256
– 1 } × 100
–1 × 100
}