DF2117VT20V Renesas Electronics America, DF2117VT20V Datasheet - Page 709

• Manufacturer Part Number: DF2117VT20V
• Description: MCU 16BIT FLASH 3V 160K 144-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2117VT20V

• Core Processor: H8S/2600
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: FIFO, I²C, LPC, SCI, SmartCard
• Peripherals: POR, PWM, WDT
• Number Of I /o: 112
• Program Memory Size: 160KB (160K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-TQFP, 144-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

20.4.4
The LPC interface can be placed in the shutdown state according to the state of the LPCPD pin.
There are two kinds of LPC interface shutdown state: LPC hardware shutdown and LPC software
shutdown. The LPC hardware shutdown state is controlled by the LPCPD pin, while the LPC
software shutdown state is controlled by the SDWNB bit. In both states, the LPC interface enters
the reset state by itself, and is no longer affected by external signals other than the LRESET and
LPCPD signals.
Placing the slave in sleep mode or software standby mode is effective in reducing current
dissipation in the shutdown state. If software standby mode is set, some means must be provided
for exiting software standby mode before clearing the shutdown state with the LPCPD signal.
If the SDWNE bit has been set to 1 beforehand, the LPC hardware shutdown state is entered at the
same time as the LPCPD signal falls, and prior preparation is not possible. If the LPC software
shutdown state is set by means of the SDWNB bit, on the other hand, the LPC software shutdown
state cannot be cleared at the same time as the rising edge of the LPCPD signal. Taking these
points into consideration, the following operating procedure uses a combination of LPC software
shutdown and LPC hardware shutdown.
1. Clear the SDWNE bit to 0.
2. Set the ERRIE bit to 1 and wait for an interrupt by the SDWN flag.
3. When an ERRI interrupt is generated by the SDWN flag, check the LPC interface internal
4. Set the SDWNB bit to 1 to set LPC software standby mode.
5. Set the SDWNE bit to 1 and make a transition to LPC hardware standby mode. The SDWNB
6. Check the state of the LPCPD signal to make sure that the LPCPD signal has not risen during
7. If software standby mode has been set, exit software standby mode by some means
8. When a rising edge is detected in the LPCPD signal, the SDWNE bit is automatically cleared
status flags and perform any necessary processing.
bit is cleared automatically.
steps 3 to 5. If the signal has risen, clear SDWNE to 0 to return to the state in step 1.
independent of the LPC.
to 0. If the slave has been placed in sleep mode, the mode is exited by means of LRESET
signal input, on completion of the LPC transfer cycle, or by some other means.
LPC Interface Shutdown Function (LPCPD)
Rev. 2.00 Sep. 28, 2009 Page 667 of 994
REJ09B0452-0200