DF2117VT20V Renesas Electronics America, DF2117VT20V Datasheet - Page 892

• Manufacturer Part Number: DF2117VT20V
• Description: MCU 16BIT FLASH 3V 160K 144-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2117VT20V

• Core Processor: H8S/2600
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: FIFO, I²C, LPC, SCI, SmartCard
• Peripherals: POR, PWM, WDT
• Number Of I /o: 112
• Program Memory Size: 160KB (160K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-TQFP, 144-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

26.3
The operating mode changes to medium-speed mode as soon as the current bus cycle ends by the
settings of the SCK2 to SCK0 bits in SBYCR. The operating clock can be selected from φ/2, φ/4,
φ/8, φ/16, or φ/32. On-chip peripheral functions other than the bus masters and the PS2 operate on
the system clock (φ).
In medium-speed mode, a bus access is executed in the specified number of states with respect to
the bus master operating clock. For example, if φ/4 is selected as the operating clock, on-chip
memory is accessed in four states, and internal I/O registers in eight states.
A transition is made from medium-speed mode to high-speed mode at the end of the current bus
cycle by clearing all of bits SCK2 to SCK0 to 0.
If the SLEEP instruction is executed when the SSBY bit in SBYCR is 0 and the LSON bit in
LPWRCR is 0, a transition is made to sleep mode. When sleep mode is canceled by an interrupt,
medium-speed mode is restored. When the SLEEP instruction is executed with the SSBY bit set to
1, the LSON bit in LPWRCR set to 0, and the PSS bit in TCSR (WDT_1) set to 0, operation shifts
to software standby mode. When software standby mode is canceled by an external interrupt,
medium-speed mode is restored.
When the RES pin is driven low and medium-speed mode is cancelled, operation shifts to the reset
state. The same applies to a reset caused by an overflow of the watchdog timer.
Figure 26.2 shows the timing of medium-speed mode.
Rev. 2.00 Sep. 28, 2009 Page 850 of 994
REJ09B0452-0200
Medium-Speed Mode
φ,
peripheral module
clock
Bus master clock
Internal address bus
Internal write signal
Figure 26.2 Timing of Medium-Speed Mode
SBYCR
Medium-speed mode
SBYCR