DF2117VT20V Renesas Electronics America, DF2117VT20V Datasheet - Page 394

• Manufacturer Part Number: DF2117VT20V
• Description: MCU 16BIT FLASH 3V 160K 144-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2117VT20V

• Core Processor: H8S/2600
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: FIFO, I²C, LPC, SCI, SmartCard
• Peripherals: POR, PWM, WDT
• Number Of I /o: 112
• Program Memory Size: 160KB (160K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-TQFP, 144-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

12.6.3
When the corresponding input capture signal is detected during reading of TDPICR in timer mode,
the input capture signal is delayed by one cycle of the system clock (φ). Figure 12.15 shows the
timing of this conflict.
12.6.4
If the edge of TDPCYI is detected in the second half of a cycle of writing to any of the upper
limit/lower limit registers (TDPPDMX, TDPPDMN, TDPWDMX, and TDPWDMN) in cycle
measurement mode, the detected edge signal is delayed by one cycle of the system clock (φ).
Figure 12.16 shows the timing of this conflict.
Rev. 2.00 Sep. 28, 2009 Page 352 of 994
REJ09B0452-0200
φ
TDPCYI
Internal write
signal
Input capture
signal
TDPCNT
TDPICR
TPDMXOVF
φ
TDPCYI
TDPICR
read signal
Input capture
signal
TDPCNT
TDPICR
ICPF
Conflict between Input Capture and TDPICR Read
Conflict between Edge Detection in Cycle Measurement Mode and Writing to the
Upper Limit or Lower Limit Register
Figure 12.16 Conflict between Edge Detection and Register Write
Figure 12.15 Conflict between Input Capture and TDPICR Read
N - 1
M
N
M
N
(Cycle Measurement Mode)
Capture occurs
Capture occurs
TDPICR > TDPPDMX (Cycle upper limit exceeded)
H'0000
N
N
N + 1
N + 2