DF2117VT20V Renesas Electronics America, DF2117VT20V Datasheet - Page 16

• Manufacturer Part Number: DF2117VT20V
• Description: MCU 16BIT FLASH 3V 160K 144-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2117VT20V

• Core Processor: H8S/2600
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: FIFO, I²C, LPC, SCI, SmartCard
• Peripherals: POR, PWM, WDT
• Number Of I /o: 112
• Program Memory Size: 160KB (160K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-TQFP, 144-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Rev. 2.00 Sep. 28, 2009 Page xiv of xl
REJ09B0452-0200
Item
18.4.5 Slave Receive
Operation
Figure 18.15 Example
of Slave Receive Mode
Operation Timing (2)
(MLS = 0)
19.3.2 Keyboard Buffer
Control Register 2
(KBCR2)
19.3.6 Keyboard Buffer
Transmit Data Register
(KBTR)
19.4.1 Receive
Operation
Figure 19.3 Sample
Receive Processing
Flowchart
19.4.9 KCLK Fall
Interrupt Operation
Figure 19.14 Example
of KCLK Input Fall
Interrupt Operation
19.5.4 Medium-Speed
Mode
Page
573
593
598
565
608
614
Revision (See Manual for Details)
Figure amended
Table amended
Table amended
Figure amended
Note amended
Note: * The KBF setting timing is the same as the timing of
Description amended
In medium-speed mode, the PS2 operates with the medium-
speed clock. For normal operation of the PS2, set the medium-
speed clock to a frequency of 300 kHz or higher.
Bit
7 to 4
Description
Keyboard Buffer Transmit Data Register 7 to 0
Initialized to H'FF at reset.
Bit Name
—
KBF setting and KCLK automatic I/O inhibit bit
generation in figure 19.11. When the KBF bit is used
as the KCLK input fall interrupt flag, the automatic I/O
inhibit function does not operate.
User processing
Receive enabled state
ICDRR
and KDI bits both
Set KBE bit
Initial
Value
All 1
KCLKI
1?
Data (n-2)
Yes
R/W
R/W
[9] Set ACKB=1
[8] IRIC clear
Description
Reserved
These bits are always read as 1. The initial value
should not be changed.
No
[3]
[10] ICDR read (Data (n-1))
Keyboard side in data
Execute receive abort
transmission state.
processing.
Data (n-1)