DF2117VT20V Renesas Electronics America, DF2117VT20V Datasheet - Page 545

• Manufacturer Part Number: DF2117VT20V
• Description: MCU 16BIT FLASH 3V 160K 144-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2117VT20V

• Core Processor: H8S/2600
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: FIFO, I²C, LPC, SCI, SmartCard
• Peripherals: POR, PWM, WDT
• Number Of I /o: 112
• Program Memory Size: 160KB (160K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-TQFP, 144-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

17.3.9
FLCR sets formats of the transmit/receive data.
Bit
7
6
5
4
3
Bit Name
DLAB
BREAK
STICK
PARITY
EPS
PEN
Line Control Register (FLCR)
0
Initial Value
0
0
0
0
R/W
R/W
R/W
R
R/W
R/W
FDLL and FDLH are placed at the same addresses
as the FRBR/FTHR and FIER addresses. This bit
selects which register is to be accessed.
0: FRBR/FTHR and FIER access enabled
1: FDLL and FDLH access enabled
Generates a break by driving the serial output signal
FTxD low.
The break state is released by clearing this bit.
0: Break released
1: Break generated
These bits are not supported in this LSI.
These bits are always read as 0 and cannot be
modified.
Selects even or odd parity when the PEN bit is 1.
0: Odd parity
1: Even parity
Selects whether to add a parity bit for data
transmission and whether to perform a parity check
for data reception.
0: No parity bit added/parity check disabled
1: Parity bit added/parity check enabled
Description
Divisor Latch Address
Break Control
Stick Parity
Parity Select
Parity Enable
Rev. 2.00 Sep. 28, 2009 Page 503 of 994
REJ09B0452-0200