DF2117VT20V Renesas Electronics America, DF2117VT20V Datasheet - Page 571

• Manufacturer Part Number: DF2117VT20V
• Description: MCU 16BIT FLASH 3V 160K 144-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2117VT20V

• Core Processor: H8S/2600
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: FIFO, I²C, LPC, SCI, SmartCard
• Peripherals: POR, PWM, WDT
• Number Of I /o: 112
• Program Memory Size: 160KB (160K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-TQFP, 144-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

This LSI has a three-channel I
subset of the Philips I
controls the I
18.1
• Selection of addressing format or non-addressing format
• Conforms to Philips I
• Two ways of setting slave address (I
• Start and stop conditions generated automatically in master mode (I
• Selection of the acknowledge output level in reception (I
• Automatic loading of an acknowledge bit in transmission (I
• Wait function in master mode (I
• Wait function (I
• Interrupt sources
⎯ I
⎯ Clocked synchronous serial format: non-addressing format without an acknowledge bit, for
⎯ A wait can be inserted by driving the SCL pin low after data transfer, excluding
⎯ The wait can be cleared by clearing the interrupt flag.
⎯ A wait request can be generated by driving the SCL pin low after data transfer.
⎯ The wait request is cleared when the next transfer becomes possible.
⎯ Data transfer end (including when a transition to transmit mode with I
⎯ Address match: When any slave address matches or the general call address is received in
⎯ Arbitration lost
⎯ Start condition detection (in master mode)
⎯ Stop condition detection (in slave mode)
master operation only
acknowledgement.
when ICDR data is transferred from ICDRT to ICDRS or from ICDRS to ICDRR, or
during a wait state)
slave receive mode with I
arbitration)
2
C bus format: addressing format with an acknowledge bit, for master/slave operation
Features
2
C bus differs partly from the Philips configuration, however.
2
C bus format)
Section 18 I
2
C bus (inter-IC bus) interface functions. The register configuration that
2
C bus interface (I
2
C bus interface. The I
2
C bus format (including address reception after loss of master
2
C bus format)
2
C bus format)
2
2
C Bus Interface (IIC)
C bus format)
2
C bus interface conforms to and provides a
2
C bus format)
Rev. 2.00 Sep. 28, 2009 Page 529 of 994
2
C bus format)
Section 18 I
2
C bus format)
2
C bus format occurs,
2
C Bus Interface (IIC)
REJ09B0452-0200