DF2117VT20V Renesas Electronics America, DF2117VT20V Datasheet - Page 346

• Manufacturer Part Number: DF2117VT20V
• Description: MCU 16BIT FLASH 3V 160K 144-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2117VT20V

• Core Processor: H8S/2600
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: FIFO, I²C, LPC, SCI, SmartCard
• Peripherals: POR, PWM, WDT
• Number Of I /o: 112
• Program Memory Size: 160KB (160K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-TQFP, 144-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

10.8.11 Conflict between TCNT Write and Overflow/Underflow
If there is an up-count or down-count in the T
overflow/underflow occurs, the TCNT write takes precedence and the TCFV/TCFU flag in TSR is
not set. Figure 10.52 shows the operation timing when there is conflict between TCNT write and
overflow.
10.8.12 Multiplexing of I/O Pins
In this LSI, the TCLKA input pin is multiplexed with the TIOCC0 I/O pin, the TCLKB input pin
with the TIOCD0 I/O pin, the TCLKC input pin with the TIOCB1 I/O pin, and the TCLKD input
pin with the TIOCB2 I/O pin. When an external clock is input, compare match output should not
be performed from a multiplexed pin.
10.8.13 Module Stop Mode Setting
TPU operation can be enabled or disabled by the module stop control register. In the initial state,
TPU operation is disabled. Access to TPU registers is enabled when module stop mode is
cancelled. For details, see section 26, Power-Down Modes.
Rev. 2.00 Sep. 28, 2009 Page 304 of 994
REJ09B0452-0200
Figure 10.52 Conflict between TCNT Write and Overflow
φ
Address
Write signal
TCNT
TCFV flag
H'FFFF
TCNT write cycle
T1
2
TCNT address
state of a TCNT write cycle, and
T2
M
TCNT write data