DF2117VT20V Renesas Electronics America, DF2117VT20V Datasheet - Page 558

• Manufacturer Part Number: DF2117VT20V
• Description: MCU 16BIT FLASH 3V 160K 144-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2117VT20V

• Core Processor: H8S/2600
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: FIFO, I²C, LPC, SCI, SmartCard
• Peripherals: POR, PWM, WDT
• Number Of I /o: 112
• Program Memory Size: 160KB (160K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-TQFP, 144-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

17.4.3
(1)
Use an example of the flowchart in figure 17.3 to initialize the SCIF before transmitting or
receiving data.
Rev. 2.00 Sep. 28, 2009 Page 516 of 994
REJ09B0452-0200
Initialization of the SCIF
Initialization of the SCIF
Set data transfer format in FLCR
Set interrupt enable bits in FIER
Clear DLAB bit in FLCR to 0
Set DLAB bit in FLCR to 1
Set FDLH and FDLL
Clear module stop
End of Initialization
Start initialization
FIFOs used?
Set SCIFCR
Figure 17.3 Example of Initialization Flowchart
No
Yes
[1]
[2]
[3]
[4]
[5]
[9]
Set receive FIFO trigger level in FFCR
Set XMITFRST and RCVRFRST bits
in FFCR to 1 to reset FIFOs
Set FIFOE bit in FFCR to 1
[1]
[2]
[3]
[4]
[5]
[6]
[7]
[8]
[9]
Select an input clock with the CKSEL1 and
CKSEL0 bits in SCIFCR. Set the SCIF input/
output pins with the SCIFOE1 and SCIFOE0
bits in SCIFCR.
Set the DLAB bit in FLCR to 1 to enable
access to FDLL and FDLH.
The initial value of FDLL and FDLH is 0.
Set a value within the range from 1 to 65535.
Clear the DLAB bit in FLCR to 0 to disable
access to FDLL and FDLH.
Select parity with the EPS and PEN bits in
FLCR, and set the stop bit with the STOP bit
in FLCR. Then, set the data length with the
CLS1 and CLS0 bits in FLCR.
When FIFOs are used, set the FIFOE bit in
FFCR to 1.
Set the receive FIFO trigger level with the
RCVRTRIG1 and RCVRTRIG0 bits in FFCR.
Set the XMITFRST and RCVRFRST bits in
FFCR to 1 to reset the FIFOs.
Enable or disable an interrupt with the
EDSSI, ELSI, ETBEI, and ERBFI bits in
FIER and the OUT2 bit in FMCR.
[6]
[7]
[8]