DF2117VT20V Renesas Electronics America, DF2117VT20V Datasheet - Page 38

• Manufacturer Part Number: DF2117VT20V
• Description: MCU 16BIT FLASH 3V 160K 144-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2117VT20V

• Core Processor: H8S/2600
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: FIFO, I²C, LPC, SCI, SmartCard
• Peripherals: POR, PWM, WDT
• Number Of I /o: 112
• Program Memory Size: 160KB (160K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-TQFP, 144-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

20.4 Operation ........................................................................................................................... 660
20.5 Interrupt Sources................................................................................................................ 674
20.6 Usage Note......................................................................................................................... 678
Section 21 FSI Interface ......................................................................................681
21.1 Features.............................................................................................................................. 681
21.2 Input/Output Pins............................................................................................................... 683
21.3 Register Description........................................................................................................... 684
Rev. 2.00 Sep. 28, 2009 Page xxxvi of xl
REJ09B0452-0200
20.3.4 Host Interface Control Register 5 (HICR5) .......................................................... 630
20.3.5 LPC Channel 1 Address Registers H and L (LADR1H and LADR1L)................ 631
20.3.6 LPC Channel 2 Address Registers H and L (LADR2H and LADR2L)................ 632
20.3.7 LPC Channel 3 Address Registers H and L (LADR3H and LADR3L)................ 634
20.3.8 LPC Channel 4 Address Registers H and L (LADR4H and LADR4L)................ 636
20.3.9 Input Data Registers 1 to 4 (IDR1 to IDR4) ......................................................... 637
20.3.10 Output Data Registers 1 to 4 (ODR1 to ODR4) ................................................... 637
20.3.11 Bidirectional Data Registers 0 to 15 (TWR0 to TWR15)..................................... 638
20.3.12 Status Registers 1 to 4 (STR1 to STR4) ............................................................... 638
20.3.13 SERIRQ Control Register 0 (SIRQCR0).............................................................. 645
20.3.14 SERIRQ Control Register 1 (SIRQCR1).............................................................. 649
20.3.15 SERIRQ Control Register 2 (SIRQCR2).............................................................. 653
20.3.16 SERIRQ Control Register 3 (SIRQCR3).............................................................. 656
20.3.17 SERIRQ Control Register 4 (SIRQCR4).............................................................. 657
20.3.18 SCIF Address Register (SCIFADRH, SCIFADRL) ............................................. 658
20.3.19 Host Interface Select Register (HISEL)................................................................ 659
20.4.1 LPC interface Activation ...................................................................................... 660
20.4.2 LPC I/O Cycles..................................................................................................... 661
20.4.3 Gate A20............................................................................................................... 664
20.4.4 LPC Interface Shutdown Function (LPCPD)........................................................ 667
20.4.5 LPC Interface Serialized Interrupt Operation (SERIRQ) ..................................... 671
20.4.6 LPC Interface Clock Start Request ....................................................................... 673
20.4.7 SCIF Control from LPC Interface......................................................................... 673
20.5.1 IBFI1, IBFI2, IBFI3, IBFI4, OBEI, and ERRI ..................................................... 674
20.5.2 SMI, HIRQ1, HIRQ3, HIRQ4, HIRQ5, HIRQ6, HIRQ7, HIRQ8, HIRQ9,
20.6.1 Data Conflict......................................................................................................... 678
21.3.1 FSI Control Register 1 (FSICR1) ......................................................................... 686
21.3.2 FSI Control Register 2 (FSICR2) ......................................................................... 688
21.3.3 FSI Byte Count Register (FSIBNR) ..................................................................... 689
21.3.4 FSI Instruction Register (FSIINS) ........................................................................ 690
21.3.5 FSI Instruction Register (FSIRDINS)................................................................... 691
HIRQ10, HIRQ11, HIRQ12, HIRQ13, HIRQ14, and HIRQ15............................ 675