DF2117VT20V Renesas Electronics America, DF2117VT20V Datasheet - Page 486

MCU 16BIT FLASH 3V 160K 144-TQFP

DF2117VT20V

Manufacturer Part Number
DF2117VT20V
Description
MCU 16BIT FLASH 3V 160K 144-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2100r
Datasheet

Specifications of DF2117VT20V

Core Processor
H8S/2600
Core Size
16-Bit
Speed
20MHz
Connectivity
FIFO, I²C, LPC, SCI, SmartCard
Peripherals
POR, PWM, WDT
Number Of I /o
112
Program Memory Size
160KB (160K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 16x10b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
144-TQFP, 144-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DF2117VT20V
Manufacturer:
Renesas
Quantity:
100
Part Number:
DF2117VT20V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Rev. 2.00 Sep. 28, 2009 Page 444 of 994
REJ09B0452-0200
Figure 15.16 Sample SCI Transmission Operation in Clocked Synchronous Mode
Synchronization
clock
Serial data
TDRE
TEND
TXI interrupt request
generated
Write transmit data to TDR and
clear TDRE flag in SSR to 0
Read TDRE flag in SSR
Read TEND flag in SSR
Clear TE bit in SCR to 0
All data transmitted?
Start transmission
End transmission
Figure 15.17 Sample Serial Transmission Flowchart
Initialization
TDRE = 1
TEND = 1
Yes
Yes
Yes
Data written to TDR and
TDRE flag cleared to 0 in
TXI interrupt service
routine
Bit 0
Transfer direction
Bit 1
1 frame
No
No
No
[3]
[4]
[2]
[1]
Bit 7
TXI interrupt request
generated
[1] SCI initialization:
[2] SCI status check and transmit data
[3] Serial transmission continuation
Note:
Bit 0
The TxD pin is automatically
designated as the transmit data
output pin.
write:
Read SSR and check that the TDRE
flag is set to 1, then write transmit
data to TDR and clear the TDRE flag
to 0.
procedure:
To continue serial transmission, be
sure to read 1 from the TDRE flag to
confirm that writing is possible, then
write data to TDR, and then clear the
TDRE flag to 0.
Do not write to SMR, SCR,
BRR, and SDCR from the
start to the end of
transmission except the
process of [4].
Bit 1
TEI interrupt request
generated
Bit 6
Bit 7

Related parts for DF2117VT20V