HD64F2239TF20I Renesas Electronics America, HD64F2239TF20I Datasheet
HD64F2239TF20I
Specifications of HD64F2239TF20I
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HD64F2239TF20I Summary of contents
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To our customers, Old Company Name in Catalogs and Other Documents st On April 1 , 2010, NEC Electronics Corporation merged with Renesas Technology Corporation, and Renesas Electronics Corporation took over all the business of both companies. Therefore, although the ...
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All information included in this document is current as of the date this document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas Electronics products listed herein, please confirm ...
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The revision list can be viewed directly by clicking the title page. The revision list summarizes the locations of revisions and additions. Details should always be checked by referring to the relevant text. H8S/2258, H8S/2239, H8S/2238, H8S/2237, H8S/2227 Groups Hardware ...
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This document is provided for reference purposes only so that Renesas customers may select the appropriate Renesas products for their use. Renesas neither makes warranties or representations with respect to the accuracy or completeness of the information contained in ...
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General Precautions in the Handling of MPU/MCU Products The following usage notes are applicable to all MPU/MCU products from Renesas. For detailed usage notes on the products covered by this manual, refer to the relevant sections of the manual. If ...
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Configuration of This Manual This manual comprises the following items: 1. General Precautions in the Handling of MPU/MCU Products 2. Configuration of This Manual 3. Preface 4. Main Revisions for This Edition The list of revisions is a summary of ...
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The H8S/2558 Group, H8S/2239 Group, H8S/2238 Group, H8S/2237 Group, and H8S/2227 Group are high-performance microcomputers made up of the internal 32-bit configuration H8S/2000 CPU as their cores, and the peripheral functions required to configure a system. A single-power flash memory ...
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List of On-Chip Peripheral Functions: H8S/2258 Group Name Group H8S/2258 Microcomputer H8S/2256 Bus controller (BSC) O (16 bits) Data transfer controller O (DTC) ⎯ DMA controller (DMAC) PC break controller (PBC) ×2 ×6 16-bit timer pulse unit (TPU) ×4 8-bit ...
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Notes on reading this manual: • In order to understand the overall functions of the chip Read the manual according to the contents. This manual can be roughly categorized into descriptions on the CPU, system control functions, peripheral functions, and ...
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User's Manuals for Development Tools: Document Title H8S, H8/300 Series C/C++ Compiler, Assembler, Optimized Linkage Editor User's Manual High-performance Embedded Workshop User's Manual Application Notes: Document Title H8S, H8/300 Series C/C++ Compiler Package Application Note Rev. 6.00 Mar. 18, 2010 ...
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Main Revisions for This Edition Item 1.3.2 Pin Arrangements in Each Mode Table 1.1 Pin Arrangements in Each Mode of H8S/2258 Group Table 1.2 Pin Arrangements in Each Mode of H8S/2239 Group Table 1.3 Pin Arrangements in Each Mode of ...
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Item 2.3 Address Space Figure 2.5 Memory Map 2.6 Instruction Set Table 2.1 Instruction Classification 2.6.1 Table of Instructions Classified by Function Table 2.3 Data Transfer Instructions Rev. 6.00 Mar. 18, 2010 Page REJ09B0054-0600 Page Revision (See ...
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Item 4.8 Usage Note Figure 4.3 Operation When SP Value Is Odd 5.6.5 IRQ Interrupt 5.6.6 NMI Interrupts Usage Notes 6.3.4 Operation in Transitions to Power-Down Modes 7.6.4 Wait Control (2) Pin Wait Insertion 9.2.5 DTC Transfer Count Register A ...
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Item 10.2.2 Port 3 Data Register (P3DR) 10.4.2 Port 7 Data Register (P7DR) 10.6.2 Port A Data Register (PADR) 10.7.2 Port B Data Register (PBDR) 10.8.2 Port C Data Register (PCDR) Rev. 6.00 Mar. 18, 2010 Page xii of lx ...
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Item 10.9.2 Port D Data Register (PDDR) 10.10.2 Port E Data Register (PEDR) 10.11.2 Port F Data Register (PFDR) 10.12.2 Port G Data Register (PGDR) 10.13 Handling of Unused Pins Page Revision (See Manual for Details) 344 Table amended Bit ...
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Item 11.3.1 Timer Control Register (TCR) 13.3.1 Timer Counter (TCNT) 13.6.3 Changing Value of PSS or CKS2 to CKS0 13.6.7 Notes on Initializing TCNT by Using the TME Bit 15.3.8 Smart Card Mode Register (SCMR) Rev. 6.00 Mar. 18, 2010 ...
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Item 2 16.3 Bus Control Register (ICCR) 16.4.6 Slave Transmit Operation 16.6 Usage Notes 2 Table 16 Bus Timing (SCL and SDA Output) Page Revision (See Manual for Details) 644 Table amended Initial Bit Bit Name ...
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Item 16.6 Usage Notes Figure 16.22 Flowchart and Timing of Start Condition Instruction Issuance for Retransmission Figure 16.23 Timing of Stop Condition Issuance Figure 16.25 ICDR Read and ICCR Access Timing in Slave Transmit Mode 17.2 Input/Output Pins Table 17.1 ...
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Item 17.8.4 Range of Analog Power Supply and Other Pin Settings 27.3.2 DC Characteristics Table 27.14 DC Characteristics (1) 27.3.4 A/D Conversion Characteristics Table 27.23 A/D Conversion Characteristics 27.5.2 DC Characteristics Table 27.39 DC Characteristics (1) Page Revision (See Manual ...
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Item 27.5.2 DC Characteristics Table 27.39 DC Characteristics (1) 27.5.4 A/D Conversion Characteristics Table 27.47 A/D Conversion Characteristics 27.6.2 DC Characteristics Table 27.51 DC Characteristics (1) Rev. 6.00 Mar. 18, 2010 Page xviii of lx REJ09B0054-0600 Page Revision (See Manual ...
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Item 27.6.4 A/D Conversion Characteristics Table 27.57 A/D Conversion Characteristics Appendix B Product Codes Table B.3 Product Codes of H8S/2238 Group Page Revision (See Manual for Details) 944 Table condition amended Condition A (ZTAT version 2 ...
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Item Appendix B Product Codes Table B.3 Product Codes of H8S/2238 Group Appendix C Product Codes Figure C.1 TFP-100B Package Dimensions Figure C.2 TFP-100G Package Dimensions Figure C.3 FP-100A Package Dimensions Figure C.4 FP-100B Package Dimensions Figure C.5 BP-112 Package ...
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Section 1 Overview............................................................................................. 1 1.1 Features ............................................................................................................................... 1 1.2 Internal Block Diagram....................................................................................................... 4 1.3 Pin Description.................................................................................................................... 9 1.3.1 Pin Arrangement .................................................................................................... 9 1.3.2 Pin Arrangements in Each Mode .........................................................................20 1.3.3 Pin Functions .......................................................................................................44 Section 2 CPU................................................................................................... 63 2.1 Features .............................................................................................................................63 ...
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Program-Counter Relative—@(d:8, PC) or @(d:16, PC)......................................92 2.7.8 Memory Indirect—@@aa:8 ..................................................................................93 2.7.9 Effective Address Calculation ...............................................................................94 2.8 Processing States.................................................................................................................96 2.9 Usage Notes ........................................................................................................................98 2.9.1 TAS Instruction......................................................................................................98 2.9.2 STM/LDM Instruction ...........................................................................................98 2.9.3 Bit Manipulation Instructions ................................................................................98 2.9.4 Access Methods for Registers ...
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Register Descriptions ........................................................................................................129 5.3.1 Interrupt Priority Registers and O (IPRA to IPRL, IPRO) ......................130 5.3.2 IRQ Enable Register (IER) ..................................................................................131 5.3.3 IRQ Sense Control Registers H and L (ISCRH and ISCRL) ...............................131 5.3.4 IRQ Status Register ...
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CMFA and CMFB ............................................................................................... 163 6.4.4 PC Break Interrupt when DTC and DMAC Is Bus Master .................................. 163 6.4.5 PC Break Set for Instruction Fetch at Address Following BSR, JSR, JMP, TRAPA, RTE, and RTS Instruction..................................................................... 163 6.4.6 I ...
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Operation .............................................................................................................199 7.10.2 Bus Transfer Timing ............................................................................................200 7.10.3 External Bus Release Usage Note........................................................................200 7.11 Resets and the Bus Controller ...........................................................................................201 Section 8 DMA Controller (DMAC) ................................................................ 203 8.1 Features .............................................................................................................................203 8.2 Input/Output Pins .............................................................................................................. 205 8.3 Register Descriptions ........................................................................................................205 ...
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Medium-Speed Mode........................................................................................... 277 Activation by Falling Edge on DREQ Pin ........................................................... 278 8.7.4 8.7.5 Activation Source Acceptance............................................................................. 278 8.7.6 Internal Interrupt after End of Transfer................................................................ 278 8.7.7 Channel Re-Setting .............................................................................................. 279 Section 9 Data Transfer Controller (DTC) ........................................................281 9.1 ...
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Port 1 Data Direction Register (P1DDR).............................................................309 10.1.2 Port 1 Data Register (P1DR)................................................................................310 10.1.3 Port 1 Register (PORT1)......................................................................................310 10.1.4 Pin Functions .......................................................................................................311 10.2 Port 3.................................................................................................................................315 10.2.1 Port 3 Data Direction Register (P3DDR).............................................................315 10.2.2 Port 3 Data Register (P3DR)................................................................................316 10.2.3 Port ...
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Port C Pull-Up MOS Control Register (PCPCR) ................................................ 341 10.8.5 Pin Functions ....................................................................................................... 342 10.8.6 Input Pull-Up MOS States in Port C.................................................................... 342 10.9 Port D................................................................................................................................ 343 10.9.1 Port D Data Direction Register (PDDDR) ........................................................... 343 10.9.2 Port D ...
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Timer Start Register (TSTR)................................................................................396 11.3.9 Timer Synchronous Register (TSYR) ..................................................................397 11.4 Operation...........................................................................................................................398 11.4.1 Basic Functions....................................................................................................398 11.4.2 Synchronous Operation........................................................................................403 11.4.3 Buffer Operation ..................................................................................................405 11.4.4 Cascaded Operation .............................................................................................409 11.4.5 PWM Modes ........................................................................................................411 11.4.6 Phase Counting Mode ..........................................................................................416 11.5 Interrupt Sources ...............................................................................................................423 ...
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Timer Control/Status Register (TCSR)................................................................ 447 12.4 Operation .......................................................................................................................... 452 12.4.1 Pulse Output......................................................................................................... 452 12.5 Operation Timing.............................................................................................................. 453 12.5.1 TCNT Incrementation Timing ............................................................................. 453 12.5.2 Timing of CMFA and CMFB Setting when a Compare-Match Occurs .............. 454 12.5.3 Timing of ...
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Contention between Timer Counter (TCNT) Write and Increment .....................478 13.6.3 Changing Value of PSS or CKS2 to CKS0..........................................................479 13.6.4 Switching between Watchdog Timer Mode and Interval Timer Mode................479 13.6.5 Internal Reset in Watchdog Timer Mode.............................................................479 13.6.6 OVF Flag Clearing ...
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Slave Receive Operation...................................................................................... 529 14.4.3 Master Reception ................................................................................................. 533 14.4.4 Slave Transmission .............................................................................................. 536 14.5 Interrupt Sources............................................................................................................... 540 14.6 Usage Notes ...................................................................................................................... 541 14.6.1 Setting Module Stop Mode .................................................................................. 541 14.6.2 TxRDY Flag and Underrun Error ........................................................................ 541 14.6.3 ...
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Multiprocessor Serial Data Reception..................................................................599 15.6 Operation in Clocked Synchronous Mode ........................................................................602 15.6.1 Clock....................................................................................................................602 15.6.2 SCI Initialization (Clocked Synchronous Mode) .................................................602 15.6.3 Serial Data Transmission (Clocked Synchronous Mode) ....................................603 15.6.4 Serial Data Reception (Clocked Synchronous Mode)..........................................606 15.6.5 Simultaneous Serial Data ...
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Serial Control Register X (SCRX)....................................................................... 643 2 16.3 Bus Control Register (ICCR) ......................................................................... 644 2 16.3 Bus Status Register (ICSR)............................................................................ 649 16.3.8 DDC Switch Register (DDCSWR) ...................................................................... 653 16.4 Operation .......................................................................................................................... 653 2 16.4.1 I ...
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Notes on Noise Countermeasures ........................................................................705 Section 18 D/A Converter................................................................................. 707 18.1 Features .............................................................................................................................707 18.2 Input/Output Pins .............................................................................................................. 708 18.3 Register Description..........................................................................................................708 18.3.1 D/A Data Registers 0 and 1 (DADR0 and DADR1)............................................708 18.3.2 D/A Control Register (DACR) ............................................................................709 18.4 Operation...........................................................................................................................710 ...
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Programmer Mode ............................................................................................................ 743 20.12 Power-Down States for Flash Memory............................................................................. 745 20.13 Flash Memory Programming and Erasing Precautions..................................................... 745 20.14 Note on Switching from F-ZTAT Version to Masked ROM Version .............................. 751 Section 21 Masked ROM ..................................................................................753 21.1 Features............................................................................................................................. ...
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Medium-Speed Mode........................................................................................................790 24.3 Sleep Mode .......................................................................................................................791 24.3.1 Transition to Sleep Mode.....................................................................................791 24.3.2 Exiting Sleep Mode..............................................................................................792 24.4 Software Standby Mode....................................................................................................792 24.4.1 Transition to Software Standby Mode .................................................................792 24.4.2 Clearing Software Standby Mode ........................................................................792 24.4.3 Oscillation Settling Time after Clearing Software ...
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Power Supply Connection for H8S/2239 Group, H8S/2238R, H8S/2236R, H8S/2237 Group, and H8S/2227 Group (No Internal Power Supply Step-Down Circuit) ................ 804 25.4 Note on Bypass Capacitor................................................................................................. 805 Section 26 List of Registers...............................................................................807 26.1 Register Addresses (In Address Order)............................................................................. 807 ...
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Absolute Maximum Ratings ................................................................................927 27.6.2 DC Characteristics ...............................................................................................928 27.6.3 AC Characteristics ...............................................................................................937 27.6.4 A/D Conversion Characteristics...........................................................................944 27.6.5 D/A Conversion Characteristics...........................................................................945 27.6.6 Flash Memory Characteristics .............................................................................946 27.7 Operating Timing..............................................................................................................948 27.7.1 Clock Timing .......................................................................................................948 27.7.2 Control Signal Timing .........................................................................................949 27.7.3 Bus ...
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Section 1 Overview Figure 1.1 Internal Block Diagram of H8S/2258 Group ......................................................... 4 Figure 1.2 Internal Block Diagram of H8S/2239 Group ......................................................... 5 Figure 1.3 Internal Block Diagram of H8S/2238 Group ......................................................... 6 Figure 1.4 Internal Block Diagram of H8S/2237 ...
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Figure 2.9 General Register Data Formats (2)......................................................................... 77 Figure 2.10 Memory Data Formats ........................................................................................... 78 Figure 2.11 Instruction Formats (Examples) ............................................................................. 90 Figure 2.12 Branch Address Specification in Memory Indirect Mode...................................... 93 Figure 2.13 State Transitions..................................................................................................... 97 Figure 2.14 Flowchart ...
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Figure 7.2 Overview of Area Divisions................................................................................. 175 CSn Signal Output Timing ( ................................................................ 178 Figure 7.3 Figure 7.4 On-5Chip Memory Access Cycle ........................................................................ 179 Figure 7.5 Pin States during On-Chip Memory Access......................................................... 179 Figure 7.6 On-Chip ...
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Figure 8.15 Operation in Block Transfer Mode (BLKDIR = 1)..............................................253 Figure 8.16 Operation Flow in Block Transfer Mode .............................................................254 Figure 8.17 Example of Block Transfer Mode Setting Procedure...........................................255 Figure 8.18 Example of DMA Transfer Bus Timing...............................................................256 Figure 8.19 Example of ...
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Figure 9.12 DTC Operation Timing (Example of Chain Transfer) ......................................... 299 Section 10 I/O Ports Figure 10.1 Types of Open Drain Outputs .............................................................................. 318 Section 11 16-Bit Timer Pulse Unit (TPU) Figure 11.1 Block Diagram of TPU (H8S/2258 Group, H8S/2239 ...
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Figure 11.34 Input Capture Input Signal Timing ......................................................................428 Figure 11.35 Counter Clear Timing (Compare Match) .............................................................428 Figure 11.36 Counter Clear Timing (Input Capture) .................................................................429 Figure 11.37 Buffer Operation Timing (Compare Match) ........................................................429 Figure 11.38 Buffer Operation Timing (Input Capture) ............................................................430 ...
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Figure 13.3 Interval Timer Mode Operation ........................................................................... 475 Figure 13.4 Timing of OVF Setting ........................................................................................ 475 Figure 13.5 Timing of WOVF Setting..................................................................................... 476 Figure 13.6 Writing to TCNT, TCSR...................................................................................... 477 Figure 13.7 Writing to RSTCSR ............................................................................................. 478 Figure 13.8 Contention ...
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Figure 15.10 Sample Serial Transmission Flowchart ................................................................591 Figure 15.11 Example of SCI Operation in Reception (Example with 8-Bit Data, Parity, One Stop Bit) .................................................592 Figure 15.12 Sample Serial Reception Data Flowchart (1) .......................................................594 Figure 15.12 Sample Serial Reception Data Flowchart ...
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Figure 15.44 Operation when Switching from SCK Pin Function to Port Pin Function (Example of Preventing Low-Level Output)........................................................ 631 2 Section Bus Interface (IIC) (Option) Figure 16.1 Block Diagram Figure 16 Bus ...
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Section 17 A/D Converter Figure 17.1 Block Diagram of A/D Converter ........................................................................690 Figure 17.2 Access to ADDR (When Reading H'AA40) ........................................................696 Figure 17.3 Example of A/D converter Operation (Single Mode, Channel 1 Selected)..........698 Figure 17.4 Example of A/D Converter Operation ...
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Section 22 PROM Figure 22.1 HD6472237 Socket Adapter Pin Correspondence Diagram (FP-100B, TFP-100B, TFP-100G)....................................................................... 756 Figure 22.2 HD6472237 Socket Adapter Pin Correspondence Diagram (FP-100A) .............. 757 Figure 22.3 Memory Map in PROM Mode ............................................................................. 758 Figure 22.4 High-Speed Programming Flowchart................................................................... ...
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Figure 27.5 Power Supply Voltage and Operating Ranges (H8S/2237 Group and H8S/2227 Group).............................................................843 Figure 27.6 Output Load Circuit .............................................................................................853 2 Figure 27 Bus Interface Input/Output Timing (Optional)...............................................859 Figure 27.8 Output Load Circuit .............................................................................................873 Figure 27.9 Output Load Circuit ...
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Section 1 Overview Table 1.1 Pin Arrangements in Each Mode of H8S/2258 Group ........................................... 20 Table 1.2 Pin Arrangements in Each Mode of H8S/2239 Group ........................................... 24 Table 1.3 Pin Arrangements in Each Mode of H8S/2238 Group ........................................... 29 Table ...
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Section 5 Interrupt Controller Table 5.1 Pin Configuration ...................................................................................................129 Table 5.2 Interrupt Sources, Vector Addresses, and Interrupt Priorities ................................137 Table 5.3 Interrupt Control Modes.........................................................................................142 Table 5.4 Interrupts Selected in Each Interrupt Control Mode (1) .........................................143 Table 5.5 Interrupts Selected in ...
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Table 9.7 Number of States Required for Each Execution Status .......................................... 300 Section 10 I/O Ports Table 10.1 Port Functions ........................................................................................................ 306 Table 10.2 Input Pull-Up MOS States in Port A ...................................................................... 332 Table 10.3 Input Pull-Up MOS States in ...
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Table 11.29 Cascaded Combinations .........................................................................................409 Table 11.30 PWM Output Registers and Output Pins................................................................412 Table 11.31 Clock Input Pins in Phase Counting Mode.............................................................416 Table 11.32 Up/Down-Count Conditions in Phase Counting Mode 1 .......................................418 Table 11.33 Up/Down-Count Conditions in Phase Counting Mode ...
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Table 15.10 Serial Transfer Formats (Asynchronous Mode) ..................................................... 586 Table 15.11 SSR Status Flags and Receive Data Handling........................................................ 593 Table 15.12 Interrupt Sources of Serial Communication Interface Mode.................................. 623 Table 15.13 Interrupt Sources in Smart Card Interface Mode.................................................... 624 2 ...
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Table 22.2 Socket Adapters......................................................................................................758 Table 22.3 Mode Selection in PROM Mode ............................................................................759 Table 22.4 DC Characteristics in PROM Mode .......................................................................761 Table 22.5 AC Characteristics in PROM Mode .......................................................................762 Section 23 Clock Pulse Generator Table 23.1 Damping Resistance Value.....................................................................................771 Table 23.2 ...
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Table 27.8 Timing of On-Chip Peripheral Modules................................................................. 857 2 Table 27 Bus Timing....................................................................................................... 858 Table 27.10 A/D Conversion Characteristics ............................................................................. 860 Table 27.11 D/A Conversion Characteristics ............................................................................. 861 Table 27.12 Flash Memory Characteristics................................................................................ 862 Table 27.13 Absolute Maximum ...
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Table 27.42 Clock Timing..........................................................................................................916 Table 27.43 Control Signal Timing............................................................................................917 Table 27.44 Bus Timing.............................................................................................................918 Table 27.45 Timing of On-Chip Peripheral Modules.................................................................920 2 Table 27. Bus Timing .......................................................................................................922 Table 27.47 A/D Conversion Characteristics .............................................................................923 Table 27.48 D/A Conversion Characteristics .............................................................................924 ...
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Rev. 6.00 Mar. 18, 2010 Page REJ09B0054-0600 ...
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Features • High-speed H8S/2000 central processing unit with an internal 16-bit architecture ⎯ Upward-compatible with H8/300 and H8/300H CPUs on an object level ⎯ Sixteen 16-bit general registers ⎯ 65 basic instructions • Various peripheral functions ⎯ PC break ...
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Section 1 Overview • On-chip memory ROM Model Flash memory HD64F2258 version HD64F2239 HD64F2238B HD64F2238R HD64F2227 PROM version HD6472237 Masked ROM HD6432258 version HD6432258W HD6432256 HD6432256W HD6432239 HD6432239W HD6432238B HD6432238BW HD6432238R HD6432238RW HD6432236B HD6432236BW HD6432236R HD6432236RW HD6432237 HD6432235 HD6432233 HD6432227 ...
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Compact package (Code) * Package TQFP-100 TFP-100B, TFP-100BV TQFP-100 * 1 TFP-100G, TFP-100GV QFP-100 * 2 FP-100A, FP-100AV QFP-100 * 3 FP-100B, FP-100BV LFBGA-112 * 4 BP-112, BP-112V TFBGA-112 * 5 TBP-112A, TBP-112AV Notes: 1. Not supported by the ...
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Section 1 Overview 1.2 Internal Block Diagram Figures 1.1 to 1.5 show the internal block diagrams. MD2 MD1 MD0 EXTAL XTAL OSC1 OSC2 STBY RES NMI FWE PF7/φ PF6/AS PF5/RD PF4/HWR PF3/LWR/ADTRG/IRQ3 PF2/WAIT PF1/BACK/BUZZ PF0/BREQ/IRQ2 PG4/CS0 PG3/CS1 PG2/CS2 PG1/CS3/IRQ7 PG0/IRQ6 ...
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MD2 MD1 MD0 EXTAL XTAL OSC1 OSC2 STBY RES NMI FWE PF7/φ PF6/AS PF5/RD PF4/HWR PF3/LWR/ADTRG/IRQ3 PF2/WAIT PF1/BACK/BUZZ PF0/BREQ/IRQ2 PG4/CS0 PG3/CS1 PG2/CS2 PG1/CS3/IRQ7 PG0/IRQ6 Port 1 Figure 1.2 Internal Block Diagram of H8S/2239 Group Port D H8S/2000 CPU DMAC Interrupt ...
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Section 1 Overview MD2 MD1 MD0 EXTAL XTAL OSC1 OSC2 STBY RES NMI FWE PF7/φ PF6/AS PF5/RD PF4/HWR PF3/LWR/ADTRG/IRQ3 PF2/WAIT PF1/BACK/BUZZ PF0/BREQ/IRQ2 PG4/CS0 PG3/CS1 PG2/CS2 PG1/CS3/IRQ7 PG0/IRQ6 Figure 1.3 Internal Block Diagram of H8S/2238 Group Rev. 6.00 Mar. 18, 2010 ...
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MD2 MD1 MD0 EXTAL XTAL OSC1 OSC2 STBY RES NMI FWE PF7/φ PF6/AS PF5/RD PF4/HWR PF3/LWR/ADTRG/IRQ3 PF2/WAIT PF1/BACK/BUZZ PF0/BREQ/IRQ2 PG4/CS0 PG3/CS1 PG2/CS2 PG1/CS3/IRQ7 PG0/IRQ6 Figure 1.4 Internal Block Diagram of H8S/2237 Group Port D H8S/2000 CPU Interrupt controller DTC PC ...
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Section 1 Overview MD2 MD1 MD0 EXTAL XTAL OSC1 OSC2 STBY RES NMI FWE PF7/ φ PF6/AS PF5/RD PF4/HWR PF3/LWR/ADTRG/IRQ3 PF2/WAIT PF1/BACK/BUZZ PF0/BREQ/IRQ2 PG4/CS0 PG3/CS1 PG2/CS2 PG1/CS3/IRQ7 PG0/IRQ6 Figure 1.5 Internal Block Diagram of H8S/2227 Group Rev. 6.00 Mar. 18, ...
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Pin Description 1.3.1 Pin Arrangement (1) Pin Arrangement of H8S/2258 Group Figures 1.6 and 1.7 show the pin arrangement of the H8S/2258 Group. P30/TxD0 76 P31/RxD0 77 P32/SCK0/SDA1/IRQ4 78 P33/TxD1/SCL1 79 P34/RxD1/SDA0 80 P35/SCK1/SCL0/IRQ5 81 82 P36 P77/TxD3 83 ...
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Section 1 Overview P32/SCK0/SDA1/IRQ4 81 P33/TxD1/SCL1 82 P34/RxD1/SDA0 83 P35/SCK1/SCL0/IRQ5 84 P36 85 P77/TxD3 86 P76/RxD3 87 P75/TMO3/SCK3 88 P74/TMO2/MRES 89 P73/TMO1/CS7 90 P72/TMO0/CS6 91 P71/TMRI23/TMCI23/CS5 92 P70/TMRI01/TMCI01/CS4 93 PG0/IRQ6 94 PG1/CS3/IRQ7 95 PG2/Tx/CS2 96 PG3/Rx/CS1 97 PG4/CS0 98 PE0/D0 ...
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Pin Arrangement of H8S/2239 Group Figures 1.8 and 1.9 show the pin arrangement of the H8S/2239 Group. P30/TxD0 76 P31/RxD0 77 P32/SCK0/SDA1/IRQ4 78 P33/TxD1/SCL1 79 P34/RxD1/SDA0 80 P35/SCK1/SCL0/IRQ5 81 P36 82 P77/TxD3 83 P76/RxD3 84 P75/TMO3/SCK3 85 P74/TMO2/MRES 86 ...
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Section 1 Overview A B PF1/ NC PF4/ BACK/ 11 HWR (Reserve) BUZZ NC P30/ PF2/ 10 WAIT (Reserve) TxD0 P32/ P33/ PF0/ SCK0/ BREQ/ TxD1/ 9 SDA1/ IRQ2 SCL1 IRQ4 P35/ P34/ SCK1/ P36 RxD1/ 8 SCL0/ SDA0 IRQ5 ...
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Pin Arrangement of H8S/2238 Group Figures 1.10 to 1.12 show the pin arrangement of the H8S/2238 Group. P30/TxD0 76 P31/RxD0 77 P32/SCK0/SDA1/IRQ4 78 79 P33/TxD1/SCL1 P34/RxD1/SDA0 80 P35/SCK1/SCL0/IRQ5 81 P36 82 P77/TxD3 83 P76/RxD3 84 P75/TMO3/SCK3 85 86 P74/TMO2/MRES ...
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Section 1 Overview P32/SCK0/SDA1/IRQ4 81 P33/TxD1/SCL1 82 P34/RxD1/SDA0 83 P35/SCK1/SCL0/IRQ5 84 P36 85 P77/TxD3 86 P76/RxD3 87 P75/TMO3/SCK3 88 P74/TMO2/MRES 89 P73/TMO1/CS7 90 P72/TMO0/CS6 91 P71/TMRI23/TMCI23/CS5 92 P70/TMRI01/TMCI01/CS4 93 PG0/IRQ6 94 PG1/CS3/IRQ7 95 PG2/CS2 96 PG3/CS1 97 PG4/CS0 98 PE0/D0 ...
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PF1/ PF4/ BACK HWR BUZZ P30/ PF2/ NC WAIT PF5/RD 10 TxD0 P32/ P33/ PF0/ SCK0/ BREQ/ 9 TxD1/ SDA1/ IRQ2 SCL1 IRQ4 P35/ P34/ SCK1/ 8 P36 RxD1/ SCL0/ SDA0 IRQ5 P75/ P74/ P76/ ...
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Section 1 Overview (4) Pin Arrangement of H8S/2237 Group Figures 1.13 and 1.14 show the pin arrangement of the H8S/2237 Group. P30/TxD0 76 P31/RxD0 77 P32/SCK0/IRQ4 78 79 P33/TxD1 P34/RxD1 80 P35/SCK1/IRQ5 81 P36 82 P77/TxD3 83 P76/RxD3 84 P75/SCK3 ...
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P32/SCK0/IRQ4 81 P33/TxD1 82 P34/RxD1 83 P35/SCK1/IRQ5 84 P36 85 P77/TxD3 86 P76/RxD3 87 P75/SCK3 88 P74/MRES 89 P73/TMO1/CS7 90 P72/TMO0/CS6 91 P71/CS5 92 P70/TMRI01/TMCI01/CS4 93 PG0/IRQ6 94 PG1/CS3/IRQ7 95 PG2/CS2 96 PG3/CS1 97 PG4/CS0 98 PE0/D0 99 PE1/D1 100 ...
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Section 1 Overview (5) Pin Arrangement of H8S/2227 Group Figures 1.15 and 1.16 show the pin arrangement of the H8S/2227 Group. P30/TxD0 76 P31/RxD0 77 P32/SCK0/IRQ4 78 P33/TxD1 79 P34/RxD1 80 P35/SCK1/IRQ5 81 P36 82 P77/TxD3 83 P76/RxD3 84 P75/SCK3 ...
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P32/SCK0/IRQ4 81 P33/TxD1 82 P34/RxD1 83 P35/SCK1/IRQ5 84 P36 85 P77/TxD3 86 87 P76/RxD3 P75/SCK3 88 P74/MRES 89 90 P73/TMO1/CS7 P72/TMO0/CS6 91 P71/CS5 92 93 P70/TMRI01/TMCI01/CS4 PG0/IRQ6 94 PG1/CS3/IRQ7 95 96 PG2/CS2 PG3/CS1 97 PG4/CS0 98 PE0/D0 99 PE1/D1 100 ...
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Section 1 Overview 1.3.2 Pin Arrangements in Each Mode Tables 1.1 to 1.5 show the pin arrangements in each mode. Table 1.1 Pin Arrangements in Each Mode of H8S/2258 Group Pin No. TFP- 100B FP- FP- 100B 100A Mode 4 ...
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Pin No. TFP- 100B FP- FP- 100B 100A Mode PB4/A12/ TIOCA4 27 30 PB5/A13/ TIOCB4 28 31 PB6/A14/ TIOCA5 29 32 PB7/A15/ TIOCB5 30 33 PA0/A16 31 34 PA1/A17/TxD2 32 35 PA2/A18/RxD2 33 36 PA3/A19/ SCK2 34 ...
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Section 1 Overview Pin No. TFP- 100B FP- FP- 100B 100A Mode P43/AN3 50 53 P42/AN2 51 54 P41/AN1 52 55 P40/AN0 53 56 Vref 54 57 AVCC 55 58 MD0 56 59 MD1 57 60 OSC2 ...
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Pin No. TFP- 100B FP- FP- 100B 100A Mode P32/SCK0/ SDA1/IRQ4 79 82 P33/TxD1/ SCL1 80 83 P34/RxD1/ SDA0 81 84 P35/SCK1/ SCL0/IRQ5 82 85 P36 83 86 P77/TxD3 84 87 P76/RxD3 85 88 P75/TMO3/ SCK3 86 ...
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Section 1 Overview Table 1.2 Pin Arrangements in Each Mode of H8S/2239 Group Pin No. TFP-100B TFP-100BV TFP-100G TFP-100GV TBP-112A * 1 FP-100B TBP-112AV * 1 FP-100BV Mode PE5/ PE6/ PE7/ ...
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Pin No. TFP-100B TFP-100BV TFP-100G TFP-100GV TBP-112A * 1 FP-100B TBP-112AV * 1 FP-100BV Mode PB5/A13/ TIOCB4 28 H4 PB6/A14/ TIOCA5 29 K3 PB7/A15/ TIOCB5 30 L3 PA0/A16 31 J4 PA1/A17/ TxD2 32 K4 PA2/A18/ RxD2 33 ...
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Section 1 Overview Pin No. TFP-100B TFP-100BV TFP-100G TFP-100GV TBP-112A * 1 FP-100B TBP-112AV * 1 FP-100BV Mode P44/AN4 49 K9 P43/AN3 50 L10 P42/AN2 51 K10 P41/AN1 52 K11 P40/AN0 53 H8 Vref 54 J10 AVCC ...
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Pin No. TFP-100B TFP-100BV TFP-100G TFP-100GV TBP-112A * 1 FP-100B TBP-112AV * 1 FP-100BV Mode 4 76 A10 P30/TxD0 77 D8 P31/RxD0 78 B9 P32/SCK0/ SDA1/IRQ4 79 A9 P33/TxD1/ SCL1 80 C8 P34/RxD1/ SDA0 81 B8 P35/SCK1/ SCL0/IRQ5 82 A8 ...
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Section 1 Overview Pin No. TFP-100B TFP-100BV TFP-100G TFP-100GV TBP-112A * 1 FP-100B TBP-112AV * 1 FP-100BV Mode PE2/ PE3/D3 100 A2 PE4/D4 Notes: Supported only by HD64F2239. 1. The NC should be left open. ...
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Table 1.3 Pin Arrangements in Each Mode of H8S/2238 Group Pin No. TFP-100B BP-112 * TFP-100BV BP-112V * TFP-100G TBP-112A * TFP-100GV FP-100A * 1 FP-100B TBP- FP-100AV * 112AV * 1 FP-100BV ...
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Section 1 Overview Pin No. TFP-100B BP-112 * TFP-100BV BP-112V * TFP-100G TBP-112A * TFP-100GV FP-100A * 1 FP-100B TBP- FP-100AV * 112AV * 1 FP-100BV ...
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Pin No. TFP-100B BP-112 * TFP-100BV BP-112V * TFP-100G TBP-112A * TFP-100GV FP-100A * 1 FP-100B TBP- FP-100AV * 112AV * 1 FP-100BV ...
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Section 1 Overview Pin No. TFP-100B BP-112 * TFP-100BV BP-112V * TFP-100G TBP-112A * TFP-100GV FP-100A * 1 FP-100B TBP- FP-100AV * 112AV * 1 FP-100BV C10 74 77 B11 ...
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Pin No. TFP-100B BP-112 * TFP-100BV BP-112V * TFP-100G TBP-112A * TFP-100GV FP-100A * 1 FP-100B TBP- FP-100AV * 112AV * 1 FP-100BV ...
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Section 1 Overview Table 1.4 Pin Arrangements in Each Mode of H8S/2237 Group Pin No. TFP-100B TFP-100BV TFP-100G TFP-100GV FP-100B FP-100A FP-100BV FP-100AV Mode PE5/ PE6/ PE7/ ...
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Pin No. TFP-100B TFP-100BV TFP-100G TFP-100GV FP-100B FP-100A FP-100BV FP-100AV Mode PB3/A11/ TIOCD3 26 29 PB4/A12/ TIOCA4 27 30 PB5/A13/ TIOCB4 28 31 PB6/A14/ TIOCA5 29 32 PB7/A15/ TIOCB5 30 33 PA0/A16 31 34 PA1/A17/ TxD2 32 ...
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Section 1 Overview Pin No. TFP-100B TFP-100BV TFP-100G TFP-100GV FP-100B FP-100A FP-100BV FP-100AV Mode P16/ TIOCA2/ IRQ1 41 44 P17/ TIOCB2/ TCLKD 42 45 AVSS 43 46 P97/DA1 44 47 P96/DA0 45 48 P47/AN7 46 49 P46/AN6 ...
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Pin No. TFP-100B TFP-100BV TFP-100G TFP-100GV FP-100B FP-100A FP-100BV FP-100AV Mode FWE 67 70 MD2 68 71 PF7/φ HWR PF3/LWR/ ADTRG/ IRQ3 73 76 PF2/WAIT 74 77 ...
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Section 1 Overview Pin No. TFP-100B TFP-100BV TFP-100G TFP-100GV FP-100B FP-100A FP-100BV FP-100AV Mode P72/TMO0/ CS6 89 92 P71/CS5 90 93 P70/ TMRI01/ TMCI01/ CS4 91 94 PG0/IRQ6 92 95 PG1/CS3/ IRQ7 93 96 PG2/CS2 94 97 ...
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Table 1.5 Pin Arrangements in Each Mode of H8S/2227 Group Pin No. TFP-100B TFP-100BV TFP-100G TFP-100GV FP-100B * FP-100A * 1 2 FP-100BV * 1 FP-100AV * 2 Mode PE5/ PE6/ PE7/D7 4 ...
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Section 1 Overview Pin No. TFP-100B TFP-100BV TFP-100G TFP-100GV FP-100B * FP-100A * 1 2 FP-100BV * 1 FP-100AV * 2 Mode PB4/A12 27 30 PB5/A13 28 31 PB6/A14 29 32 PB7/A15 30 33 PA0/A16 31 34 ...
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Pin No. TFP-100B TFP-100BV TFP-100G TFP-100GV FP-100B * FP-100A * 1 2 FP-100BV * 1 FP-100AV * 2 Mode P97 44 47 P96 45 48 P47/AN7 46 49 P46/AN6 47 50 P45/AN5 48 51 P44/AN4 49 52 ...
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Section 1 Overview Pin No. TFP-100B TFP-100BV TFP-100G TFP-100GV FP-100B * FP-100A * 1 2 FP-100BV * 1 FP-100AV * 2 Mode 4 HWR PF3/LWR/ ADTRG/ IRQ3 73 76 PF2/WAIT 74 77 PF1/BACK/ BUZZ 75 78 ...
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Pin No. TFP-100B TFP-100BV TFP-100G TFP-100GV FP-100B * FP-100A * 1 2 FP-100BV * 1 FP-100AV * 2 Mode PG1/CS3/ IRQ7 93 96 PG2/CS2 94 97 PG3/CS1 95 98 PG4/CS0 96 99 PE0/D0 97 100 PE1/D1 98 ...
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Section 1 Overview 1.3.3 Pin Functions Table 1.6 lists the pin functions of the H8S/2258 Group. Table 1.7 lists the pin functions of the H8S/2239 Group and H8S/2238 Group. Table 1.8 lists the pin functions of the H8S/2237 Group and ...
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TFP-100B TFP-100BV FP-100B Type Symbol FP-100BV Clock OSC2 57 φ 68 Operating MD2 67 mode MD1 56 control MD0 55 RES * System 59 control MRES 86 STBY * 61 BREQ 75 BACK 74 FWE 66 NMI * Interrupts 60 ...
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Section 1 Overview TFP-100B TFP-100BV FP-100B Type Symbol FP-100BV Data bus D15 to 100 to 96 CS7 Bus 87 CS6 control 88 CS5 89 CS4 90 CS3 92 CS2 93 CS1 94 CS0 ...
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TFP-100B TFP-100BV FP-100B Type Symbol FP-100BV 16-bit timer- TIOCA3 22 pulse unit TIOCB3 23 (TPU) TIOCC3 24 TIOCD3 25 TIOCA4 26 TIOCB4 27 TIOCA5 28 TIOCB5 29 8-bit timer TMO3 TMO0 TMCI23 89 TMCI01 90 TMRI23 ...
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Section 1 Overview TFP-100B TFP-100BV FP-100B Type Symbol FP-100BV Tx IEBus 93 controller Rx 94 (IEB) A/D AN7 converter AN0 ADTRG 72 D/A DA1 43 converter DA0 44 A/D AVCC 54 converter, D/A converter AVSS 42 ...
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TFP-100B TFP-100BV FP-100B Type Symbol FP-100BV I/O ports PC7 15, 13 PC0 PD7 PD0 PE7 to 100 to 96 100, 99, PE0 PF7 PF0 PG4 to ...
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Section 1 Overview Table 1.7 Pin Functions of H8S/2239 Group and H8S/2238 Group TFP-100B TFP-100BV TFP-100G TFP-100GV FP-100B Type Symbol FP-100BV Power VCC 62 supply CVCC 12 VSS 14 64 Clock XTAL 63 EXTAL 65 OSC1 58 Rev. 6.00 Mar. ...
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TFP-100B TFP-100BV TFP-100G TFP-100GV FP-100B Type Symbol FP-100BV Clock OSC2 57 φ 68 Operating MD2 67 mode MD1 56 control MD0 55 RES * 5 System 59 control MRES 86 STBY * 5 61 BREQ 75 BACK 74 FWE 66 ...
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Section 1 Overview TFP-100B TFP-100BV TFP-100G TFP-100GV FP-100B Type Symbol FP-100BV Address bus A23 15 Data bus D15 to 100 to 96 CS7 Bus 87 CS6 control 88 CS5 89 CS4 ...
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TFP-100B TFP-100BV TFP-100G TFP-100GV FP-100B Type Symbol FP-100BV DREQ1 DMA 89 DREQ0 controller 90 (DMAC TEND1 87 TEND0 88 DACK1 35 DACK0 34 16-bit timer- TCLKD 41 pulse unit TCLKC 39 (TPU) TCLKB 37 TCLKA 36 TIOCA0 34 ...
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Section 1 Overview TFP-100B TFP-100BV TFP-100G TFP-100GV FP-100B Type Symbol FP-100BV 8-bit timer TMO3 TMO0 TMCI23 89 TMCI01 90 TMRI23 89 TMRI01 90 Watchdog BUZZ 74 timer (WDT) Serial TxD3 83 communi- TxD2 31 cation TxD1 ...
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TFP-100B TFP-100BV TFP-100G TFP-100GV FP-100B Type Symbol FP-100BV D/A DA1 43 converter DA0 44 A/D AVCC 54 converter, D/A converter AVSS 42 Vref 53 I/O ports P17 P10 P36 P30 P47 to ...
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Section 1 Overview TFP-100B TFP-100BV TFP-100G TFP-100GV FP-100B Type Symbol FP-100BV I/O ports PC7 15, 1324 to 18, PC0 PD7 PD0 PE7 to 100 to 96, 3 PE0 to 1 PF7 to 75 ...
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Table 1.8 Pin Functions of H8S/2237 Group and H8S/2227 Group TFP-100B TFP-100BV TFP-100G TFP-100GV FP-100B * FP-100BV * Type Symbol Power supply VCC 12 62 VSS 14 64 Clock XTAL 63 EXTAL 65 OSC1 58 OSC2 57 φ 68 Operating ...
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Section 1 Overview TFP-100B TFP-100BV TFP-100G TFP-100GV FP-100B * FP-100BV * Type Symbol BREQ System 75 control BACK 74 FEW 66 NMI * 3 Interrupts 60 IRQ7 92 IRQ6 91 IRQ5 81 IRQ4 78 IRQ3 72 IRQ2 75 IRQ1 40 ...
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TFP-100B TFP-100BV TFP-100G TFP-100GV FP-100B * FP-100BV * Type Symbol LWR Bus control 72 WAIT 73 16-bit timer- TCLKD 41 pulse unit TCLKC 39 (TPU) TCLKB 37 TCLKA 36 TIOCA0 34 TIOCB0 35 TIOCC0 36 TIOCD0 37 TIOCA1 38 TIOCB1 ...
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Section 1 Overview TFP-100B TFP-100BV TFP-100G TFP-100GV FP-100B * FP-100BV * Type Symbol Serial TxD3 83 communi- TxD2 31 cation TxD1 79 interface TxD0 76 (SCI)/ RxD3 84 smart card RxD2 32 interface RxD1 80 RxD0 77 SCK3 85 SCK2 ...
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TFP-100B TFP-100BV TFP-100G TFP-100GV FP-100B * FP-100BV * Type Symbol I/O ports P47 P40 P77 P70 P97 43 P96 44 PA3 PA0 PB7 PB0 ...
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Section 1 Overview Rev. 6.00 Mar. 18, 2010 Page 62 of 982 REJ09B0054-0600 ...
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The H8S/2000 CPU is a high-speed central processing unit with an internal 32-bit architecture that is upward-compatible with the H8/300 and H8/300H CPUs. The H8S/2000 CPU has sixteen 16-bit general registers, can address a 16-Mbyte linear address space, and is ...
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Section 2 CPU • High-speed operation ⎯ All frequently-used instructions execute in one or two states ⎯ 8/16/32-bit register-register add/subtract : 1 state ⎯ 8 × 8-bit register-register multiply ⎯ 16 ÷ 8-bit register-register divide ⎯ 16 × 16-bit register-register ...
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Differences from H8/300 CPU In comparison to the H8/300 CPU, the H8S/2000 CPU has the following enhancements: • More general registers and control registers ⎯ Eight 16-bit expanded registers, and one 8-bit and two 32-bit control registers, have been ...
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Section 2 CPU 2.2 CPU Operating Modes The H8S/2000 CPU has two operating modes: normal and advanced. Normal mode supports a maximum 64-kbyte address space. Advanced mode supports a maximum 16-Mbyte total address space. The mode is selected by the ...
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H'0000 H'0001 H'0002 H'0003 H'0004 H'0005 H'0006 H'0007 H'0008 H'0009 H'000A H'000B Figure 2.1 Exception Vector Table (Normal Mode) SP (16 bits) (a) Subroutine Branch Notes: 1. When EXR is not used it is not stored on the stack. 2. ...
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Section 2 CPU • Instruction Set All instructions and addressing modes can be used. • Exception Vector Table and Memory Indirect Branch Addresses In advanced mode, the top area starting at H'00000000 is allocated to the exception vector table in ...
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Stack Structure In advanced mode, when the program counter (PC) is pushed onto the stack in a subroutine call, and the PC, condition-code register (CCR), and extended control register (EXR) are pushed onto the stack in exception handling, they ...
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Section 2 CPU 2.3 Address Space Figure 2.5 shows a memory map of the H8S/2000 CPU. The H8S/2000 CPU provides linear access to a maximum 64-kbyte address space in normal mode, and a maximum 16-Mbyte (architecturally 4-Gbyte) address space in ...
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Register Configuration The H8S/2000 CPU has the internal registers shown in figure 2.6. There are two types of registers: general registers and control registers. Control registers are a 24-bit program counter (PC), an 8-bit extended control register (EXR), and ...
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Section 2 CPU 2.4.1 General Registers The H8S/2000 CPU has eight 32-bit general registers. These general registers are all functionally alike and can be used as both address registers and data registers. When a general register is used as a ...
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SP (ER7) 2.4.2 Program Counter (PC) This 24-bit counter indicates the address of the next instruction the CPU will execute. The length of all CPU instructions is 2 bytes (one word), so the least significant PC bit is ignored (When ...
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Section 2 CPU 2.4.4 Condition-Code Register (CCR) This 8-bit register contains internal CPU status information, including an interrupt mask bit (I) and half-carry (H), negative (N), zero (Z), overflow (V), and carry (C) flags. Operations can be performed on the ...
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Bit Bit Name Initial Value 2 Z undefined 1 V undefined 0 C undefined 2.4.5 Initial Values of CPU Registers Reset exception handling loads the CPU’s program counter (PC) from the vector table, clears the trace bit in EXR to ...
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Section 2 CPU 2.5 Data Formats The H8S/2000 CPU can process 1-bit, 4-bit (BCD), 8-bit (byte), 16-bit (word), and 32-bit (longword) data. Bit-manipulation instructions operate on 1-bit data by accessing bit 2,… byte ...
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Data Type Register Number Word data Rn Word data En 15 MSB Longword data ERn 31 MSB En Legend: ERn: General register ER En: General register E Rn: General register R General register RH RnH: RnL: General register RL MSB: ...
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Section 2 CPU 2.5.2 Memory Data Formats Figure 2.10 shows the data formats in memory. The H8S/2000 CPU can access word data and longword data in memory, but word or longword data must begin at an even address ...
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Instruction Set The H8S/2000 CPU has 65 types of instructions. The instructions are classified by function in table 2.1. Table 2.1 Instruction Classification Function Instructions Data transfer MOV POP * 1 , PUSH * LDM * , STM * ...
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Section 2 CPU 2.6.1 Table of Instructions Classified by Function Tables 2.3 to 2.10 summarize the instructions in each functional category. The notation used in tables 2.3 to 2.10 is defined below. Table 2.2 Operation Notation Symbol Description General register ...
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Table 2.3 Data Transfer Instructions Size * 1 Instruction Function (EAs) → Rd, Rs → (EAd) MOV B/W/L Moves data between two general registers or between a general register and memory, or moves immediate data to a general register. MOVFPE ...
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Section 2 CPU Table 2.4 Arithmetic Operations Instructions Size * 1 Instruction Function Rd ± Rs → Rd, Rd ± #IMM → Rd ADD B/W/L Performs addition or subtraction on data in two general registers SUB immediate data ...
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Size * 1 Instruction Function Rd ÷ Rs → Rd DIVXS B/W Performs signed division on data in two general registers: either 16 bits ÷ 8 bits → 8-bit quotient and 8-bit remainder or 32 bits ÷ 16 bits → ...
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Section 2 CPU Table 2.5 Logic Operations Instructions Size * Instruction Function Rd ∧ Rs → Rd, Rd ∧ #IMM → Rd AND B/W/L Performs a logical AND operation on a general register and another general register or immediate data. ...
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Table 2.7 Bit Manipulation Instructions Size * Instruction Function 1 → (<bit-No.> of <EAd>) BSET B Sets a specified bit in a general register or memory operand to 1. The bit number is specified by 3-bit immediate data or the ...
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Section 2 CPU Size * Instruction Function C ⊕ (<bit-No.> of <EAd>) → C BXOR B XORs the carry flag with a specified bit in a general register or memory operand and stores the result in the carry flag. C ...
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Table 2.8 Branch Instructions Instruction Size Function ⎯ Bcc Branches to a specified address if a specified condition is true. The branching conditions are listed below. Mnemonic BRA(BT) BRN(BF) BHI BLS BCC(BHS) BCS(BLO) BNE BEQ BVC BVS BPL BMI BGE ...
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Section 2 CPU Table 2.9 System Control Instructions Size * Instruction Function ⎯ TRAPA Starts trap-instruction exception handling. ⎯ RTE Returns from an exception-handling routine. ⎯ SLEEP Causes a transition to a power-down state. (EAs) → CCR, (EAs) → EXR ...
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Table 2.10 Block Data Transfer Instructions Instruction Size Function ⎯ if R4L ≠ 0 then EEPMOV.B else next; ⎯ ≠ 0 then EEPMOV.W else next; Transfers a data block. Starting from the address set in ER5, transfers data ...
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Section 2 CPU (1) Operation field only (2) Operation field and register fields op (3) Operation field, register fields, and effective address extension op (4) Operation field, effective address extension, and condition field op Figure 2.11 Instruction Formats (Examples) 2.7 ...
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Register Direct—Rn The register field of the instruction specifies an 8-, 16-, or 32-bit general register containing the operand. R0H to R7H and R0L to R7L can be specified as 8-bit registers and ...
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Section 2 CPU To access data, the absolute address should be 8 bits (@aa:8), 16 bits (@aa:16 bits (@aa:32) long. For an 8-bit absolute address, the upper 24 bits are all assumed (H'FFFF). For a ...
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Memory Indirect—@@aa:8 This mode can be used by the JMP and JSR instructions. The instruction code contains an 8-bit absolute address specifying a memory operand. This memory operand contains a branch address. The upper bits of the absolute address ...
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Section 2 CPU 2.7.9 Effective Address Calculation Table 2.13 indicates how effective addresses are calculated in each addressing mode. In normal mode the upper 8 bits of the effective address are ignored in order to generate a 16-bit address. Table ...
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Addressing Mode and Instruction Format Absolute address Immediate disp Memory indirect @@aa:8 • Nomal Mode * • Advanced extended modes Note: * Normal mode is not available in this LSI. Effective Address Calculation PC contents disp Sign extension H'000000 Memory ...
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Section 2 CPU 2.8 Processing States The H8S/2000 CPU has five main processing states: the reset state, exception handling state, program execution state, bus-released state, and power-down state. Figure 2.13 indicates the state transitions. • Reset State In this state, ...
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Bus-released state Exception handling state RES = High, MRES = High 1 Reset state* From any state except hardware standby mode, a transition to the reset state occurs whenever RES Notes: 1. goes low. A transition can also be made ...
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Section 2 CPU 2.9 Usage Notes 2.9.1 TAS Instruction Only register ER0, ER1, ER4, or ER5 should be used when using the TAS instruction. The TAS instruction is not generated by the Renesas Technology H8S and H8/300 Series C/C++ compilers. ...
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The BSET, BCLR, BNOT, BST, and BIST instructions perform their operations in the following order. 1. Read the data in byte units 2. Perform the bit manipulation operation according to the instruction on the data read 3. Write the data ...
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Section 2 CPU The bit manipulation operation is performed on this value that was read. In this example, bit 4 will be cleared for H'F8. P17 I/O Output Output P1DDR 1 After bit 1 manipulation After the bit manipulation operation, ...
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Write data to the work area Write the work area data to the register that includes write-only bits Access the work area data (data transfer and bit manipulation instructions can be used) Write the work area data to the register ...
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Section 2 CPU To switch P14 from being an output pin to being an input pin, we must change the value of P1DDR bit 4 from (H'F0 → H'E0). Here, were execute a BCLR instruction for RAM0. ...
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Section 3 MCU Operating Modes 3.1 Operating Mode Selection The LSI supports four operating modes (modes 7 to 4). These operating modes are used to switch the pin functions. The operating mode is determined by the setting of the mode ...
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Section 3 MCU Operating Modes 3.2 Register Descriptions The following registers are related to the operating mode. • Mode control register (MDCR) • System control register (SYSCR) 3.2.1 Mode Control Register (MDCR) MDCR is used to monitor the current operating ...
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System Control Register (SYSCR) SYSCR is used to select the interrupt control mode and the detected edge for NMI, select the MRES input pin enable or disable, and enables or disables on-chip RAM. Bit Bit Name Initial Value R/W ...
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Section 3 MCU Operating Modes 3.3 Operating Mode Descriptions 3.3.1 Mode 4 The CPU can access a 16-Mbyte address space in advanced mode. The on-chip ROM is disabled. Pins P13 to P10, and ports A, B, and C function as ...
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Mode 6 The CPU can access a 16-Mbyte address space in advanced mode. The on-chip ROM is enabled. Pins P13 to P10, and ports A, B, and C function as input ports immediately after a reset. Address (A23 to ...
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Section 3 MCU Operating Modes 3.3.5 Pin Functions The pin functions of ports 1, and vary depending on the operating mode. Table 3.2 shows their functions in each operating mode. Table 3.2 Pin Functions in Each Operating ...
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Memory Map in Each Operating Mode Figures 3.1 to 3.9 show the memory map in each operating mode. Modes 4 and 5 (advanced extended modes with on-chip ROM disabled) H'000000 External address space H'FFB000 On-chip RAM* H'FFEFC0 External address ...
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Section 3 MCU Operating Modes Modes 4 and 5 (advanced extended modes with on-chip ROM disabled) H'000000 External address space H'FFB000 Reserved * H'FFD000 On-chip RAM * H'FFEFC0 External address space H'FFF800 Internal I/O registers H'FFFF40 External address space H'FFFF60 ...
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Modes 4 and 5 (advanced extended modes with on-chip ROM disabled) H'000000 H'000000 External address space H'060000 H'FF7000 H'FF7000 On-chip RAM* H'FFEFC0 External address H'FFEFC0 space H'FFF800 H'FFF800 Internal I/O registers External address H'FFFF40 H'FFFF40 space H'FFFF60 H'FFFF60 Internal I/O ...
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Section 3 MCU Operating Modes Modes 4 and 5 (advanced extended modes with on-chip ROM disabled) H'000000 External address space H'FFB000 On-chip RAM* H'FFEFC0 External address space H'FFF800 Internal I/O registers H'FFFF40 External address space H'FFFF60 Internal I/O registers H'FFFFC0 ...
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Modes 4 and 5 (advanced extended modes with on-chip ROM disabled) H'000000 H'000000 External address space H'020000 H'040000 H'FFB000 H'FFB000 Reserved * H'FFD000 H'FFD000 On-chip RAM * H'FFEFC0 External address H'FFEFC0 space H'FFF800 H'FFF800 Internal I/O registers H'FFFF40 External address ...
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Section 3 MCU Operating Modes Modes 4 and 5 (advanced extended modes with on-chip ROM disabled) H'000000 External address space H'FFB000 On-chip RAM* H'FFEFC0 External address space H'FFF800 Internal I/O registers External address H'FFFF40 space H'FFFF60 Internal I/O registers H'FFFFC0 ...
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Modes 4 and 5 (advanced extended modes with on-chip ROM disabled) H'000000 H'000000 Exter nal address space H'020000 H'FFB000 H'FFB000 Reserved* H'FFE000 H'FFE000 On-chip RAM* H'FFEFC0 External address H'FFEFC0 space H'FFF800 H'FFF800 Internal I/O registers External address H'FFFF40 H'FFFF40 space ...
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Section 3 MCU Operating Modes Modes 4 and 5 (advanced extended modes with on-chip ROM disabled) H'000000 External address space H'FFB000 Reserved* H'FFE000 On-chip RAM* H'FFEFC0 External address space H'FFF800 Internal I/O registers External address H'FFFF40 space H'FFFF60 Internal I/O ...
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Modes 4 and 5 (advanced extended modes with on-chip ROM disabled) H'000000 H'000000 External address space H'010000 H'020000 H'FFB000 H'FFB000 Reserved* H'FFE000 H'FFE000 On-chip RAM* H'FFEFC0 External address H'FFEFC0 space H'FFF800 H'FFF800 Internal I/O registers External address H'FFFF40 H'FFFF40 space ...
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Section 3 MCU Operating Modes Rev. 6.00 Mar. 18, 2010 Page 118 of 982 REJ09B0054-0600 ...
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Section 4 Exception Handling 4.1 Exception Handling Types and Priority As table 4.1 indicates, exception handling may be caused by a reset, trace, trap instruction, or interrupt. Exception handling is prioritized as shown in table 4.1. If two or more ...
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Section 4 Exception Handling Table 4.2 Exception Handling Vector Table Exception Source Power-on reset Manual reset Reserved for system use Trace Direct transitions * 3 External interrupt (NMI) Trap instruction (four sources) Reserved for system use External interrupt IRQ0 IRQ1 ...
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Reset A reset has the highest exception priority. When the RES or MRES pin goes low, all processing halts and this LSI enters the reset. A reset initializes the internal state of the CPU and the registers of on-chip ...
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Section 4 Exception Handling 4.3.2 Reset Exception Handling When the RES or MRES pin goes low, this LSI enters the reset. To ensure that this LSI is reset, hold the RES pin low for at least power-up. ...
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Interrupts after Reset If an interrupt is accepted after a reset and before the stack pointer (SP) is initialized, the PC and CCR will not be saved correctly, leading to a program crash. To prevent this, all interrupt requests, ...
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Section 4 Exception Handling Table 4.4 Status of CCR and EXR after Trace Exception Handling Interrupt Control Mode 0 2 Legend: 1: Set Cleared to 0 —: Retains value prior to execution 4.5 Interrupts Interrupts are controlled ...
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Table 4.5 shows the status of CCR and EXR after execution of trap instruction exception handling. Table 4.5 Status of CCR and EXR after Trap Instruction Exception Handling Interrupt Control Mode 0 2 Legend: 1: Set Cleared ...
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Section 4 Exception Handling 4.8 Usage Note When accessing word data or longword data, this LSI assumes that the lowest address bit is 0. The stack should always be accessed by word transfer instruction or longword transfer instruction, and the ...
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Section 5 Interrupt Controller 5.1 Features This LSI controls interrupts with the interrupt controller. The interrupt controller has the following features: • Two interrupt control modes ⎯ Any of two interrupt control modes can be set by means of the ...
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Section 5 Interrupt Controller A block diagram of the interrupt controller is shown in figure 5.1. INTM1, INTM0 SYSCR NMIEG NMI input IRQ input Internal interrupt request SWDTEND to TEI3 Interrupt controller Legend: IRQ sense control register ISCR: IRQ enable ...
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Input/Output Pins Table 5.1 summarizes the pins of the interrupt controller. Table 5.1 Pin Configuration Name I/O NMI Input IRQ7 Input IRQ6 Input IRQ5 Input IRQ4 Input IRQ3 Input IRQ2 Input IRQ1 Input IRQ0 Input 5.3 Register Descriptions The ...
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Section 5 Interrupt Controller • Interrupt priority register J (IPRJ) • Interrupt priority register K (IPRK) • Interrupt priority register L (IPRL) • Interrupt priority register O (IPRO) 5.3.1 Interrupt Priority Registers and O (IPRA to IPRL, ...
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IRQ Enable Register (IER) IER controls the enabling and disabling of interrupt requests IRQn ( 0). Initial Bit Bit Name Value 7 IRQ7E 0 6 IRQ6E 0 5 IRQ5E 0 4 IRQ4E 0 3 IRQ3E 0 ...
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Section 5 Interrupt Controller Initial Bit Bit Name Value 15 IRQ7SCB 0 14 IRQ7SCA 0 13 IRQ6SCB 0 12 IRQ6SCA 0 11 IRQ5SCB 0 10 IRQ5SCA 0 9 IRQ4SCB 0 8 IRQ4SCA 0 Rev. 6.00 Mar. 18, 2010 Page 132 ...
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Initial Bit Bit Name Value 7 IRQ3SCB 0 6 IRQ3SCA 0 5 IRQ2SCB 0 4 IRQ2SCA 0 3 IRQ1SCB 0 2 IRQ1SCA 0 1 IRQ0SCB 0 0 IRQ0SCA 0 R/W Description R/W IRQ3 Sense Control B IRQ3 Sense Control A ...
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Section 5 Interrupt Controller 5.3.4 IRQ Status Register (ISR) ISR indicates the status of IRQn ( interrupt requests. Initial Bit Bit Name Value 7 IRQ7F 0 6 IRQ6F 0 5 IRQ5F 0 4 IRQ4F 0 3 ...
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Interrupt Sources 5.4.1 External Interrupts There are nine external interrupts: NMI and IRQ7 to IRQ0. These interrupts can be used to restore this LSI from software standby mode. NMI Interrupt: NMI is the highest-priority interrupt, and is always accepted ...
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Section 5 Interrupt Controller IRQn input pin IRQnF Note The detection of IRQn interrupts does not depend on whether the relevant pin has been set for input or output. However, when a pin is used ...
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Table 5.2 Interrupt Sources, Vector Addresses, and Interrupt Priorities Origin of Interrupt Source Interrupt Source External Pin NMI IRQ0 IRQ1 IRQ2 IRQ3 IRQ4 IRQ5 IRQ6 IRQ7 DTC SWDTEND (completion of software initiation data transfer) Watchdog timer 0 WOVI0 (interval timer ...
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Section 5 Interrupt Controller Origin of Interrupt Source Interrupt Source TPU channel 0 TGI0D (TGR0D input capture/compare-match) TCI0V (overflow 0) ⎯ Reserved TPU channel 1 TGI1A (TGR1A input capture/compare-match) TGI1B (TGR1B input capture/compare-match) TCI1V (overflow 1) TCI1U (underflow 1) TPU ...