HD64F2239TF20I Renesas Electronics America, HD64F2239TF20I Datasheet - Page 503

• Manufacturer Part Number: HD64F2239TF20I
• Description: MCU 3V 384K I-TEMP 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2200r

Specifications of HD64F2239TF20I

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 72
• Program Memory Size: 384KB (384K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

The H8S/2258 Group, H8S/2239 Group, and H8S/2238 Group have an on-chip 8-bit timer module
with four channels (TMR_0, TMR_1, TMR_2, and TMR_3) operating on the basis of an 8-bit
counter.
The H8S/2237 Group and H8S/2227 Group have an on-chip 8-bit timer module with two channels
(TMR_0 and TMR_1) operating on the basis of an 8-bit counter.
The 8-bit timer module can be used to count external events and be used as a multifunction timer
in a variety of applications, such as generation of counter reset, interrupt requests, and pulse output
with an arbitrary duty cycle using a compare-match signal with two registers.
12.1
• Selection of clock sources
• Selection of three ways to clear the counters
• Timer output controlled by two compare-match signals
• Cascading of the two channels
• Multiple interrupt sources for each channel
• Generation of A/D conversion start trigger
Selected from three internal clocks (φ/8, φ/64, and φ/8192) and an external clock.
The counters can be cleared on compare-match A or B, or by an external reset signal.
The timer output signal in each channel is controlled by two independent compare-match
signals, enabling the timer to be used for various applications, such as the generation of pulse
output or PWM output with an arbitrary duty cycle.
⎯ TMR_0 and TMR_1 cascading
⎯ TMR_2* and TMR_3* cascading
Two compare-match interrupts and one overflow interrupt can be requested independently.
Channel 0 compare-match signal can be used as the A/D conversion start trigger.
The module can operate as a 16-bit timer using TMR_0 as the upper half and channel
TMR_1 as the lower half (16-bit count mode).
TMR_1 can be used to count TMR_0 compare-match occurrences (compare-match count
mode).
The module can operate as a 16-bit timer using TMR_2 as the upper half and channel
TMR_3 as the lower half (16-bit count mode).
TMR_3 can be used to count TMR_2 compare-match occurrences (compare-match count
mode).
Features
Section 12 8-Bit Timers
Rev. 6.00 Mar. 18, 2010 Page 441 of 982
Section 12 8-Bit Timers
REJ09B0054-0600