HD64F2239TF20I Renesas Electronics America, HD64F2239TF20I Datasheet - Page 230

• Manufacturer Part Number: HD64F2239TF20I
• Description: MCU 3V 384K I-TEMP 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2200r

Specifications of HD64F2239TF20I

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 72
• Program Memory Size: 384KB (384K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Section 7 Bus Controller
7.3.1
ABWCR designates each area for either 8-bit access or 16-bit access.
ABWCR sets the data bus width for the external memory space. The bus width for on-chip
memory and internal I/O registers is fixed regardless of the settings in ABWCR.
Note:
7.3.2
ASTCR designates each area as either a 2-state access space or a 3-state access space.
ASTCR sets the number of access states for the external memory space. The number of access
states for on-chip memory and internal I/O registers is fixed regardless of the settings in ASTCR.
Rev. 6.00 Mar. 18, 2010 Page 168 of 982
REJ09B0054-0600
Bit
7
6
5
4
3
2
1
0
Bit
7
6
5
4
3
2
1
0
Bit Name
ABW7
ABW6
ABW5
ABW4
ABW3
ABW2
ABW1
ABW0
Bit Name
AST7
AST6
AST5
AST4
AST3
AST2
AST1
AST0
* In modes 5 to 7, initial value of each bit is 1. In mode 4, initial value of each bit is 0.
Access State Control Register (ASTCR)
Bus Width Control Register (ABWCR)
Initial Value R/W
1/0*
1/0*
1/0*
1/0*
1/0*
1/0*
1/0*
1/0*
Initial Value R/W
1
1
1
1
1
1
1
1
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Description
Area 7 to 0 Bus Width Control
These bits select whether the corresponding area is to
be designated for 8-bit access or 16-bit access.
0: Area n is designated for 16-bit access
1: Area n is designated for 8-bit access
Note: n = 7 to 0
Description
Area 7 to 0 Access State Control
These bits select whether the corresponding area is to
be designated as a 2-state access space or a 3-state
access space. Wait state insertion is enabled or disabled
at the same time.
0: Area n is designated for 2-state access
1: Area n is designated for 3-state access
Note: n = 7 to 0
Wait state insertion in area n external space is
disabled
Wait state insertion in area n external space is
enabled