HD64F2239TF20I Renesas Electronics America, HD64F2239TF20I Datasheet - Page 625

• Manufacturer Part Number: HD64F2239TF20I
• Description: MCU 3V 384K I-TEMP 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2200r

Specifications of HD64F2239TF20I

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 72
• Program Memory Size: 384KB (384K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

15.3.7
SSR is a register containing status flags of the SCI and multiprocessor bits for transfer. 1 cannot
be written to flags TDRE, RDRF, ORER, PER, and FER; they can only be cleared. Some bit
functions of SSR differ between normal serial communication interface mode and Smart Card
interface mode.
• Normal Serial Communication Interface Mode (When SMIF in SCMR is 0)
Bit
7
6
Bit Name
TDRE
RDRF
Serial Status Register (SSR)
Initial
Value
1
0
R/W
R/(W) *
R/(W) *
1
1
Description
Transmit Data Register Empty
Displays whether TDR contains transmit data.
[Setting conditions]
•
•
[Clearing conditions]
•
•
Receive Data Register Full
Indicates that the received data is stored in RDR.
[Setting condition]
When serial reception ends normally and receive
data is transferred from RSR to RDR
[Clearing conditions]
•
•
The RDRF flag is not affected and retains their
previous values when the RE bit in SCR is cleared
to 0.
If reception of the next data is completed while the
RDRF flag is still set to 1, an overrun error will
occur and the receive data will be lost.
Section 15 Serial Communication Interface (SCI)
When the TE bit in SCR is 0
When data is transferred from TDR to TSR and
data can be written to TDR
When 0 is written to TDRE after reading TDRE
= 1
When the DMAC *
a TXI interrupt request and writes data to TDR
When 0 is written to RDRF after reading RDRF
= 1
When the DMAC *
an RXI interrupt and transferred data from RDR
Rev. 6.00 Mar. 18, 2010 Page 563 of 982
2
2
or the DTC *
or the DTC *
REJ09B0054-0600
3
3
is activated by
is activated by