HD64F2239TF20I Renesas Electronics America, HD64F2239TF20I Datasheet - Page 717

• Manufacturer Part Number: HD64F2239TF20I
• Description: MCU 3V 384K I-TEMP 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2200r

Specifications of HD64F2239TF20I

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 72
• Program Memory Size: 384KB (384K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

16.4.2
At startup the following procedure is used to initialize the IIC.
Note: The ICMR register should be written to only after transmit or receive operations have
16.4.3
In I
data, and the slave device returns an acknowledge signal.
2
C bus format master transmit mode, the master device outputs the transmit clock and transmit
completed.
Writing to the ICMR register while a transmit or receive operation is in progress could
cause an erroneous value to be written to bit counter bits BC2 to BC0. This could result in
improper operation.
Master Transmit Operation
Initial Setting
Set MSTPB4 = 0 (IIC0)
Transmit/receive start
Set IICE = 1 (SCRX)
Set SAR and SARX
MSTPB3 = 0 (IIC1)
Set ICE = 0 (ICCR)
Set ICE = 1 (ICCR)
Start initialization
(MSTPCRB)
Set SCRX
Set ICMR
Set ICCR
Set ICSR
Figure 16.6 Flowchart for IIC Initialization (Example)
Clear module stop.
Enable CPU access by IIC control register and data register.
Enable SAR and SARX access.
Set transfer format for 1st slave address, 2nd slave address,
and IIC (SVA8 to SVA0, FS, SVAX6 to SVAX0, FSX).
Enable IMCR and IMDR access. Use SCL and SDA pins is IIC
port.
Set acknowledge bit (ACKB).
Set transfer rate (IICX).
Set transfer format, wait insertion, and transfer rate (MLS,
WAIT, CKS2 to CKS0).
Set interrupt enable, transfer mode, and acknowledge
judgment (IEIC, MST, TRS, ACKE).
Section 16 I
Rev. 6.00 Mar. 18, 2010 Page 655 of 982
2
C Bus Interface (IIC) (Option)
REJ09B0054-0600