HD64F2239TF20I Renesas Electronics America, HD64F2239TF20I Datasheet - Page 305

• Manufacturer Part Number: HD64F2239TF20I
• Description: MCU 3V 384K I-TEMP 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2200r

Specifications of HD64F2239TF20I

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 72
• Program Memory Size: 384KB (384K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Transfer requests (activation sources) consist of A/D converter conversion end interrupts, external
requests, SCI transmit-data-empty and receive-data-full interrupts, and TPU channel 0 to 5
compare match/input capture A interrupts. External requests can only be specified for channel B.
Figure 8.8 shows an example of the setting procedure for repeat mode.
and transfer destination
Set number of transfers
Repeat mode setting
Set transfer source
Read DMABCRL
Set DMABCRH
Set DMABCRL
Repeat mode
Set DMACR
Figure 8.8 Example of Repeat Mode Setting Procedure
addresses
[1]
[2]
[3]
[4]
[5]
[6]
[1]
[2]
[3]
[4]
[5]
[6]
Set each bit in DMABCRH.
Set the transfer source address and transfer
destination address in MAR and IOAR.
Set the number of transfers in both ETCRH and
ETCRL.
Set each bit in DMACR.
Read the DTE bit in DMABCRL as 0.
Set each bit in DMABCRL.
Clear the FAE bit to 0 to select short address
mode.
Specify enabling or disabling of internal
interrupt clearing with the DTA bit.
Set the transfer data size with the DTSZ bit.
Specify whether MAR is to be incremented or
decremented with the DTID bit.
Set the RPE bit to 1.
Specify the transfer direction with the DTDIR
bit.
Select the activation source with bits DTF3 to
DTF0.
Clear the DTIE bit to 0.
Set the DTE bit to 1 to enable transfer.
Rev. 6.00 Mar. 18, 2010 Page 243 of 982
Section 8 DMA Controller (DMAC)
REJ09B0054-0600