HD64F2239TF20I Renesas Electronics America, HD64F2239TF20I Datasheet - Page 294

MCU 3V 384K I-TEMP 100-TQFP

HD64F2239TF20I

Manufacturer Part Number
HD64F2239TF20I
Description
MCU 3V 384K I-TEMP 100-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2200r
Datasheet

Specifications of HD64F2239TF20I

Core Processor
H8S/2000
Core Size
16-Bit
Speed
20MHz
Connectivity
I²C, SCI, SmartCard
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
72
Program Memory Size
384KB (384K x 8)
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
HD64F2239TF20I
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Section 8 DMA Controller (DMAC)
Table 8.3
Activation Source
Auto-request
Legend:
O:
×:
8.4.1
An interrupt request selected as a DMAC activation source can also simultaneously generate an
interrupt request for the CPU or DTC. For details, see section 5, Interrupt Controller.
With activation by an internal interrupt request, the DMAC accepts the interrupt request
independently of the interrupt controller. Consequently, interrupt controller priority settings are
irrelevant.
If the DMAC is activated by a CPU interrupt source or an interrupt request that is not used as a
DTC activation source (DTA = 1), the interrupt request flag is cleared automatically by the DMA
transfer. With ADI, TXI, and RXI interrupts, however, the interrupt source flag is not cleared
unless the relevant register is accessed in a DMA transfer. If the same interrupt is used as an
activation source for more than one channel, the interrupt request flag is cleared when the highest-
Rev. 6.00 Mar. 18, 2010 Page 232 of 982
REJ09B0054-0600
Internal
interrupts
External
requests
Can be specified
Cannot be specified
Activation by Internal Interrupt Request
ADI
TXI0
RXI0
TXI1
RXI1
TGI0A
TGI1A
TGI2A
TGI3A
TGI4A
TGI5A
DREQ pin falling edge input
DREQ pin low-level input
DMAC Activation Sources
Channels
0A and 1A
×
O
O
O
O
O
O
O
O
O
O
O
×
×
Short Address Mode
Channels
0B and 1B
×
O
O
O
O
O
O
O
O
O
O
O
O
O
Normal
Mode
O
×
×
×
×
×
×
×
×
×
×
×
O
O
Full Address Mode
Block
Transfer
Mode
×
O
O
O
O
O
O
O
O
O
O
O
O
O

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