HD64F2239TF20I Renesas Electronics America, HD64F2239TF20I Datasheet - Page 323

• Manufacturer Part Number: HD64F2239TF20I
• Description: MCU 3V 384K I-TEMP 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2200r

Specifications of HD64F2239TF20I

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 72
• Program Memory Size: 384KB (384K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Figure 8.23 shows an example of normal mode transfer activated by the DREQ pin falling edge.
DREQ pin sampling is performed every cycle, with the rising edge of the next φ cycle after the
end of the DMABCR write cycle for setting the transfer enabled state as the starting point.
When the DREQ pin low level is sampled while acceptance by means of the DREQ pin is
possible, the request is held in the DMAC. Then, when activation is initiated in the DMAC, the
request is cleared, and DREQ pin high level sampling for edge detection is started. If DREQ pin
high level sampling has been completed by the time the DMA write cycle ends, acceptance
resumes after the end of the write cycle, DREQ pin low level sampling is performed again, and
this operation is repeated until the transfer ends.
[1]
[2] [5] The request is cleared at the next bus break, and activation is started in the DMAC.
[3] [6] Start of DMA cycle; DREQ pin high level sampling on the rising edge of
[4] [7] When the DREQ pin high level has been sampled, acceptance is resumed after the write cycle
Note: In write data buffer mode, bus breaks from [2] to [7] may be hidden, and not visible.
DREQ
Address
bus
DMA
control
Channel
Figure 8.23 Example of DREQ Pin Falling Edge Activated Normal Mode Transfer
φ
Acceptance after transfer enabling; the DREQ pin low level is sampled on the rising edge of
and the request is held.
is completed.
(As in [1], the DREQ pin low level is sampled on the rising edge of
Idle
[1]
Request
Bus release
of 2 cycles
Minimum
[2]
Read
[3]
Transfer source
Request clear period
DMA
read
Write
Transfer destination
Acceptance resumes
DMA
write
Idle
[4]
Request
of 2 cycles
Minimum
release
Bus
Rev. 6.00 Mar. 18, 2010 Page 261 of 982
[5]
Read
[6]
Section 8 DMA Controller (DMAC)
Transfer source
Request clear period
DMA
read
φ
, and the request is held.)
Write
φ
starts.
Transfer destination
Acceptance resumes
DMA
write
REJ09B0054-0600
Idle
[7]
release
Bus
φ
,