HD64F2239TF20I Renesas Electronics America, HD64F2239TF20I Datasheet - Page 859

• Manufacturer Part Number: HD64F2239TF20I
• Description: MCU 3V 384K I-TEMP 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2200r

Specifications of HD64F2239TF20I

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 72
• Program Memory Size: 384KB (384K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

24.7
24.7.1
CPU operation makes a transition to watch mode when the SLEEP instruction is executed in high-
speed mode or subactive mode with SSBY in SBYCR = 1, DTON in LPWRCR = 0, and PSS in
TCSR_1 (WDT_1) = 1.
In watch mode, the CPU is stopped and peripheral modules other than WDT_1 and system clock
oscillator are also stopped. The contents of the CPU’s internal registers, the data in internal RAM,
and the statuses of the internal peripheral modules (excluding SCI and the A/D converter) and I/O
ports are retained. To make a transition to watch mode, bits SCK2 to SCK0 in SCKCR must be set
to 0.
24.7.2
Watch mode is exited by any interrupt (WOVI_1 interrupt, NMI pin, or IRQ7 to IRQ0), or signals
at the RES, MRES, or STBY pin.
• Exiting Watch Mode by Interrupts
• Exiting Watch Mode by RES Pin or MRES Pin
• Exiting Watch Mode by STBY Pin
When an interrupt occurs, watch mode is exited and a transition is made to high-speed mode or
medium-speed mode when the LPWRCR LSON bit = 0 or to subactive mode when the LSON
bit = 1. When a transition is made to high-speed mode, a stable clock is supplied to all LSI
circuits and interrupt exception processing starts after the time set in SBYCR STS2 to STS0
has elapsed. In the case of IRQ7 to IRQ0 interrupts, no transition is made from watch mode if
the corresponding enable bit/pin function switching bit has been cleared to 0, and, in the case
of interrupts from the internal peripheral modules, the interrupt enable register has been set to
disable the reception of that interrupt, or is masked by the CPU.
See section 24.4.3, Oscillation Settling Time after Clearing Software Standby Mode, for how
to set the oscillation settling time when making a transition from watch mode to high-speed
mode.
For exiting watch mode by the RES or MRES pin, see section 24.4.2, Clearing Software
Standby Mode.
When the STBY pin level is driven low, a transition is made to hardware standby mode.
Watch Mode
Transition to Watch Mode
Exiting Watch Mode
Rev. 6.00 Mar. 18, 2010 Page 797 of 982
Section 24 Power-Down Modes
REJ09B0054-0600