HD64F2239TF20I Renesas Electronics America, HD64F2239TF20I Datasheet - Page 732

• Manufacturer Part Number: HD64F2239TF20I
• Description: MCU 3V 384K I-TEMP 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2200r

Specifications of HD64F2239TF20I

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 72
• Program Memory Size: 384KB (384K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Section 16 I
In slave transmit mode, the slave device outputs the transmit data, while the master device outputs
the receive clock and returns an acknowledge signal. The transmission procedure and operations in
slave transmit mode are described below.
1. Initialize slave receive mode and wait for slave address reception.
2. When the slave address matches in the first frame following detection of the start condition,
3. After clearing the IRIC flag to 0, write data to ICDR. At this time, the TDRE internal flag is
4. The master device drives SDA low at the 9th clock pulse, and returns an acknowledge signal.
5. To continue transmission, write the next data to be transmitted into ICDR. The TDRE internal
Transmit operations can be performed continuously by repeating steps [4] and [5].
Rev. 6.00 Mar. 18, 2010 Page 670 of 982
REJ09B0054-0600
When making initial settings for slave receive mode, set the ACKE bit in ICCR to 1. This is
necessary in order to enable reception of the acknowledge bit after entering slave transmit
mode.
the slave device drives SDA low at the 9th clock pulse and returns an acknowledge signal. If
the 8th data bit (R/W) is 1, the TRS bit in ICCR is set to 1, and the mode changes to slave
transmit mode automatically. The IRIC flag is set to 1 at the rise of the 9th clock. If the IEIC
bit in ICCR has been set to 1, an interrupt request is sent to the CPU. At the same time, the
TDRE internal flag is set to 1. The slave device drives SCL low from the fall of the transmit
9th clock until ICDR data is written, to disable the master device to output the next transfer
clock.
cleared to 0. The written data is transferred to ICDRS, and the TDRE internal flag and IRIC
flag are set to 1 again. The slave device sequentially sends the data written into ICDRS in
accordance with the clock output by the master device.
The IRIC flag is cleared to 0 to detect the end of transmission. Processing from the ICDR
register writing to the IRIC flag clearing should be performed continuously. Prevent any
processing that includes interrupt processing during this period. If a duration sufficient for one
byte of data to be transferred elapses before the IRIC flag is cleared, it will not be possible to
determine that the transfer has completed.
When the value of the ACKE bit in ICSR is 1, the acknowledge signal state is stored in the
ACKB bit, so the ACKB bit can be used to determine whether the transfer operation was
performed successfully. When one frame of data has been transmitted, the IRIC flag in ICCR
is set to 1 at the rise of the 9th transmit clock pulse. When the TDRE internal flag is 0, the data
written into ICDR is transferred to ICDRS, transmission starts, and the TDRE internal flag and
IRIC flag are set to 1 again. If the TDRE internal flag has been set to 1, this slave device drives
SCL low from the fall of the 9th transmit clock until data is written to ICDR.
flag is cleared to 0. The IRIC flag is cleared to 0 to detect the end of transmission. Processing
from the ICDR writing to the IRIC flag clearing should be performed continuously. Prevent
any processing that includes interrupt processing during this period.
2
C Bus Interface (IIC) (Option)