HD64F2239TF20I Renesas Electronics America, HD64F2239TF20I Datasheet - Page 458

• Manufacturer Part Number: HD64F2239TF20I
• Description: MCU 3V 384K I-TEMP 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2200r

Specifications of HD64F2239TF20I

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 72
• Program Memory Size: 384KB (384K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Section 11 16-Bit Timer Pulse Unit (TPU)
11.3.6
The TCNT registers are 16-bit readable/writable counters. The TPU of the H8S/2227 Group has a
total of three TCNT registers, one each for channels 0 to 2. In other groups, the TPU has a total of
six TCNT registers, one each for channels 0 to 5.
The TCNT counters are initialized to H'0000 by a reset, or in hardware standby mode.
The TCNT counters cannot be accessed in 8-bit units; they must always be accessed as a 16-bit
unit.
11.3.7
The TGR registers are 16-bit readable/writable registers with a dual function as output compare
and input capture registers. The TPU of the H8S/2227 Group has a total of four TGR registers,
two for channel 0 and one each for channels 1 and 2. In other groups, the TPU has a total of eight
TGR registers, two each for channels 0 and 3, and one each for channels 1, 2, 4, and 5. TGRC and
TGRD for channels 0 and 3 can also be designated for operation as buffer registers. The TGR
registers cannot be accessed in 8-bit units; they must always be accessed as a 16-bit unit. TGR
buffer register combinations are TGRA-TGRC and TGRB-TGRD.
11.3.8
In the H8S/2227 Group, TSTR selects operate/stop for channels 0 to 2. In other groups, TSTR
selects operate/stop for channels 0 to 5. When setting the operating mode in TMDR or setting the
count clock in TCR, first stop the TCNT counter.
Note:
Rev. 6.00 Mar. 18, 2010 Page 396 of 982
REJ09B0054-0600
Bit
7, 6
5
4
3
2
1
0
* In the H8S/2227 Group, bits 5 to 3 are reserved. The write value should always be 0.
Bit Name
—
CST5 *
CST4 *
CST3 *
CST2
CST1
CST0
Timer Counter (TCNT)
Timer General Register (TGR)
Timer Start Register (TSTR)
Initial value
All 0
0
0
0
0
0
0
R/W
—
R/W
R/W
R/W
R/W
R/W
R/W
Description
Reserved
The write value should always be 0.
Counter Start 5 to 0
These bits select operation or stoppage for TCNT.
If 0 is written to the CST bit during operation with the
TIOC pin designated for output, the counter stops but
the TIOC pin output compare output level is retained.
If TIOR is written to when the CST bit is cleared to 0,
the pin output level will be changed to the set initial
output value.
0: TCNT_5 to TCNT_0 count operation is stopped
1: TCNT_5 to TCNT_0 performs count operation