HD64F2239TF20I Renesas Electronics America, HD64F2239TF20I Datasheet - Page 699

• Manufacturer Part Number: HD64F2239TF20I
• Description: MCU 3V 384K I-TEMP 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2200r

Specifications of HD64F2239TF20I

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 72
• Program Memory Size: 384KB (384K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

ICE is 1. For details on the module stop control register, refer to section 24.1.2, Module Stop
Control Registers A to C (MSTPCRA to MSTPCRC).
• I
• Slave address register_0 (SAR_0)*
• Second slave address register_0 (SARX_0)*
• I
• I
• I
• I
• Slave address register_1 (SAR_1)*
• Second slave address register_1 (SARX_1)*
• I
• I
• I
• DDC switch register (DDCSWR)
• Serial control register X (SCRX)
Note: * Some of the registers in the I
16.3.1
ICDR is an 8-bit readable/writable register that is used as a transmit data register when
transmitting and a receive data register when receiving. ICDR is divided internally into a shift
register (ICDRS), receive buffer (ICDRR), and transmit buffer (ICDRT). Data transfers among the
three registers are performed automatically in coordination with changes in the bus state, and
affect the status of internal flags such as TDRE and RDRF. When TDRE is 1 and the transmit
buffer is empty, TDRE shows that the next transmit data can be written from the CPU. When
RDRF is 1, it shows that the valid receive data is stored in the receive buffer.
If I
transmission/reception of one frame of data using ICDRS, data is transferred automatically from
ICDRT to ICDRS. If I
flag is 0) following transmission/reception of one frame of data using ICDRS, data is transferred
automatically from ICDRS to ICDRR.
If the number of bits in a frame, excluding the acknowledge bit, is less than 8, transmit data and
receive data are stored differently. Transmit data should be written justified toward the MSB side
2
C is in transmit mode and the next data is in ICDRT (the TDRE flag is 0) following
2
2
2
2
2
2
2
2
C bus data register_0 (ICDR_0)*
C bus mode register_0 (ICMR_0)*
C bus control register_0 (ICCR_0)*
C bus status register_0 (ICSR_0)*
C bus data register_1 (ICDR_1)*
C bus mode register_1 (ICMR_1)*
C bus control register_1 (ICCR_1)*
C bus status register_1 (ICSR_1)*
I
2
C Bus Data Register (ICDR)
other registers. The IICE bit in serial control register X (SCRX) selects each register.
2
C is in receive mode and no previous data remains in ICDRR (the RDRF
2
C bus interface are allocated to the same addresses of
Section 16 I
Rev. 6.00 Mar. 18, 2010 Page 637 of 982
2
C Bus Interface (IIC) (Option)
REJ09B0054-0600