HD64F2239TF20I Renesas Electronics America, HD64F2239TF20I Datasheet - Page 259

• Manufacturer Part Number: HD64F2239TF20I
• Description: MCU 3V 384K I-TEMP 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2200r

Specifications of HD64F2239TF20I

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 72
• Program Memory Size: 384KB (384K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

7.9
This LSI can release the external bus in response to a bus request from an external device. In the
external bus released state, the internal bus master continues to operate as long as there is no
external access.
In external extended mode, the bus can be released to an external device by setting the BRLE bit
in BCRL to 1. Driving the BREQ pin low issues an external bus request to this LSI. When the
BREQ pin is sampled, at the prescribed timing the BACK pin is driven low, and the address bus,
data bus, and bus control signals are placed in the high-impedance state, establishing the external
bus-released state.
In the external bus released state, an internal bus master can perform accesses using the internal
bus. When an internal bus master wants to make an external access, it temporarily defers
activation of the bus cycle, and waits for the bus request from the external bus master to be
dropped.
When the BREQ pin is driven high, the BACK pin is driven high at the prescribed timing and the
external bus released state is terminated.
In the event of simultaneous external bus release request and external access request generation,
the order of priority is as follows:
Table 7.5 shows pin states in the external bus released state.
Table 7.5
Pins
A23 to A0
D15 to D0
CSn
AS
RD
HWR
LWR
(High) External bus release > Internal bus master external access (Low)
Bus Release
Pin States in Bus Released State
Pin State
High impedance
High impedance
High impedance
High impedance
High impedance
High impedance
High impedance
Rev. 6.00 Mar. 18, 2010 Page 197 of 982
Section 7 Bus Controller
REJ09B0054-0600