HD64F2239TF20I Renesas Electronics America, HD64F2239TF20I Datasheet - Page 292

• Manufacturer Part Number: HD64F2239TF20I
• Description: MCU 3V 384K I-TEMP 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2200r

Specifications of HD64F2239TF20I

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 72
• Program Memory Size: 384KB (384K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Section 8 DMA Controller (DMAC)
chain transfer. When re-setting the control register area, perform masking by setting bits in
DMAWER to prevent modification of the contents of other channels.
Writes by the DTC to bits 15 to 12 (FAE and SAE) in DMABCR are invalid regardless of the
DMAWER settings. These bits should be changed, if necessary, by CPU processing.
In writes by the DTC to bits 7 to 4 (DTE) in DMABCR, 1 can be written without first reading 0.
To reactivate a channel set to full address mode, write 1 to both Write Enable A and Write Enable
B for the channel to be reactivated.
MAR, IOAR, and ETCR can always be written to regardless of the DMAWER settings. When
modifying these registers, the channel to be modified should be halted.
Rev. 6.00 Mar. 18, 2010 Page 230 of 982
REJ09B0054-0600
Figure 8.2 Areas for Register Re-Setting by DTC (Channel 0A)
DTC
Second transfer area
using chain transfer
First transfer area
DMACR_0A
DMACR_1A
DMAWER
MAR_0AH
MAR_0BH
MAR_1AH
MAR_1BH
MAR_0AL
ETCR_0A
MAR_0BL
ETCR_0B
MAR_1AL
ETCR_1A
MAR_1BL
ETCR_1B
IOAR_0A
IOAR_0B
IOAR_1A
IOAR_1B
DMABCR
DMACR_0B
DMACR_1B
DMATCR