HD64F2239TF20I Renesas Electronics America, HD64F2239TF20I Datasheet - Page 731

MCU 3V 384K I-TEMP 100-TQFP

HD64F2239TF20I

Manufacturer Part Number
HD64F2239TF20I
Description
MCU 3V 384K I-TEMP 100-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2200r
Datasheet

Specifications of HD64F2239TF20I

Core Processor
H8S/2000
Core Size
16-Bit
Speed
20MHz
Connectivity
I²C, SCI, SmartCard
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
72
Program Memory Size
384KB (384K x 8)
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
HD64F2239TF20I
Manufacturer:
Renesas Electronics America
Quantity:
10 000
16.4.6
If the slave address matches to the address in the first frame (address reception frame) following
the start condition detection when the 8th bit data (R/W) is 1 (read), the TRS bit in ICCR is
automatically set to 1 and the mode changes to slave transmit mode.
Figure 16.17 shows the sample flowchart for the operations in slave transmit mode.
No
Write transmit data in ICDR
No
No
Clear ACKE to 0 in ICCR
Set TRS = 0 in ICCR
Read ACKB in ICSR
Slave transmit mode
Clear IRIC in ICCR
Clear IRIC in ICCR
Clear IRIC in ICCR
Read IRIC in ICCR
Clear IRIC in ICCR
Read IRIC in ICCR
(ACKB = 0 clear)
Slave Transmit Operation
of transmission
(ACKB = 1)?
Read ICDR
IRIC = 1?
IRIC = 1?
End
End
Yes
Yes
Yes
Figure 16.17 Sample Flowchart for Slave Transmit Mode
[6] Clear IRIC in ICCR
[3], [4] Wait for 1 byte to be transmitted.
[7] Clear acknowledge bit data
[1], [2] If the slave address matches to the address in the first frame
[8] Set slave receive mode.
[3], [5] Set transmit data for the second and subsequent bytes.
[4] Determine end of transfer.
[9] Dummy read (to release the SCL line).
[10] Wait for stop condition
following the start condition detection and the R/W bit is 1 in
slave recieve mode, the mode changes to slave transmit mode.
Section 16 I
Rev. 6.00 Mar. 18, 2010 Page 669 of 982
2
C Bus Interface (IIC) (Option)
REJ09B0054-0600

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