HD64F2239TF20I Renesas Electronics America, HD64F2239TF20I Datasheet - Page 25

• Manufacturer Part Number: HD64F2239TF20I
• Description: MCU 3V 384K I-TEMP 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2200r

Specifications of HD64F2239TF20I

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 72
• Program Memory Size: 384KB (384K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

5.3
5.4
5.5
5.6
Section 6 PC Break Controller (PBC) .............................................................. 157
6.1
6.2
6.3
6.4
Register Descriptions ........................................................................................................129
5.3.1
5.3.2
5.3.3
5.3.4
Interrupt Sources ...............................................................................................................135
5.4.1
5.4.2
5.4.3
Operation...........................................................................................................................142
5.5.1
5.5.2
5.5.3
5.5.4
5.5.5
5.5.6
Usage Notes ......................................................................................................................154
5.6.1
5.6.2
5.6.3
5.6.4
5.6.5
5.6.6
Features .............................................................................................................................157
Register Descriptions ........................................................................................................158
6.2.1
6.2.2
6.2.3
6.2.4
Operation...........................................................................................................................160
6.3.1
6.3.2
6.3.3
6.3.4
6.3.5
Usage Notes ......................................................................................................................163
6.4.1
6.4.2
Interrupt Priority Registers A to L, and O (IPRA to IPRL, IPRO) ......................130
IRQ Enable Register (IER) ..................................................................................131
IRQ Sense Control Registers H and L (ISCRH and ISCRL) ...............................131
IRQ Status Register (ISR)....................................................................................134
External Interrupts ...............................................................................................135
Internal Interrupts.................................................................................................136
Interrupt Exception Handling Vector Table.........................................................136
Interrupt Control Modes and Interrupt Operation ................................................142
Interrupt Control Mode 0 .....................................................................................145
Interrupt Control Mode 2 .....................................................................................147
Interrupt Exception Handling Sequence ..............................................................148
Interrupt Response Times ....................................................................................150
DTC and DMAC Activation by Interrupt ............................................................151
Contention between Interrupt Generation and Disabling.....................................154
Instructions that Disable Interrupts ......................................................................155
When Interrupts are Disabled ..............................................................................155
Interrupts during Execution of EEPMOV Instruction..........................................155
IRQ Interrupts Usage Notes.................................................................................156
NMI Interrupts Usage Notes ................................................................................156
Break Address Register A (BARA) .....................................................................158
Break Address Register B (BARB)......................................................................159
Break Control Register A (BCRA) ......................................................................159
Break Control Register B (BCRB).......................................................................160
PC Break Interrupt Due to Instruction Fetch .......................................................160
PC Break Interrupt Due to Data Access...............................................................161
Notes on PC Break Interrupt Handling ................................................................161
Operation in Transitions to Power-Down Modes.................................................161
When Instruction Execution Is Delayed by One State .........................................162
Module Stop Mode Setting ..................................................................................163
PC Break Interrupts..............................................................................................163
Rev. 6.00 Mar. 18, 2010 Page xxiii of lx
REJ09B0054-0600