HD64F2239TF20I Renesas Electronics America, HD64F2239TF20I Datasheet - Page 350

• Manufacturer Part Number: HD64F2239TF20I
• Description: MCU 3V 384K I-TEMP 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2200r

Specifications of HD64F2239TF20I

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 72
• Program Memory Size: 384KB (384K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Section 9 Data Transfer Controller (DTC)
9.3
The DTC operates when activated by an interrupt or by a write to DTVECR by software. An
interrupt request can be directed to the CPU or DTC, as designated by the corresponding DTCER
bit. At the end of a data transfer (or the last consecutive transfer in the case of chain transfer), the
activation source or corresponding DTCER bit is cleared. The activation source flag, in the case of
RXI0, for example, is the RDRF flag of SCI_0. As there are a number of activation sources, the
activation source flag is not cleared with the last byte (or word) transfer. Take appropriate
measures at each interrupt as shown in table 9.1, Activation source and DTCER clearance.
Table 9.1
Activation
Source
Software
activation
Interrupt
activation
When an interrupt has been designated a DTC activation source, the existing CPU mask level and
interrupt controller priorities have no effect. If there is more than one activation source at the same
time, the DTC operates in accordance with the default priorities.
Figure 9.2 shows a block diagram of activation source control. For details, see section 5, Interrupt
Controller.
Rev. 6.00 Mar. 18, 2010 Page 288 of 982
REJ09B0054-0600
Activation Sources
Activation Source and DTCER Clearance
When the DISEL Bit is 0 and the
Specified Number of Transfers Have
Not Ended
•
•
•
The SWDTE bit is cleared to 0
The corresponding DTCER bit
remains set to 1
The activation source flag is cleared
to 0
When the DISEL Bit is 1,or when the
Specified Number of Transfers Have
Ended
•
•
•
•
•
The SWDTE bit remains set to 1
An interrupt is issued to the CPU
The corresponding DTCER bit is
cleared to 0
The activation source flag remains set
to 1
A request is issued to the CPU for the
activation source interrupt