HD64F2239TF20I Renesas Electronics America, HD64F2239TF20I Datasheet - Page 541

• Manufacturer Part Number: HD64F2239TF20I
• Description: MCU 3V 384K I-TEMP 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2200r

Specifications of HD64F2239TF20I

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 72
• Program Memory Size: 384KB (384K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

13.6.3
If the PSS or CKS0 to CKS2 bits in TCSR are written to while the WDT is operating, errors could
occur in the incrementation. Software must be used to stop the watchdog timer (by clearing the
TME bit to 0) before changing the value of the PSS or CKS0 to CKS2 bits.
13.6.4
If the mode is switched from watchdog timer to interval timer while the WDT is operating, errors
could occur in the incrementation. Software must be used to stop the watchdog timer (by clearing
the TME bit to 0) before switching the mode.
13.6.5
This LSI is not reset internally if TCNT overflows while the RSTE bit is cleared to 0 during
watchdog timer operation, however TCNT_0 and TCSR_0 of the WDT_0 are reset.
TCNT, TCSR, or RSTCR cannot be written to for 132 states following an overflow. During this
period, any attempt to read the WOVF flag is not acknowledged. Accordingly, wait 132 states
after overflow to write 0 to the WOVF flag for clearing.
13.6.6
When the OVF flag setting conflicts with the OVF flag reading in interval timer mode, writing 0
to the OVF bit may not clear the flag even though the OVF bit has been read while it is 1. If there
is a possibility that the OVF flag setting and reading will conflict, such as when the OVF flag is
polled with the interval timer interrupt disabled, read the OVF bit while it is 1 at least twice before
writing 0 to the OVF bit to clear the flag.
13.6.7
When the φSUB (subckock) division clock is selected as the TCNT input clock (PSS in TCSR set
to 1) and, after TME in TCSR is cleared to 0 to initialize the counter (TCNT) while the counter
(TCNT) is operating in the high-speed mode or medium-speed mode, TCNT is restarted by setting
TME to 1 once again, TCNT may not be correctly initialized.
In such cases, use either of the following methods to initialize TCNT:
(1) Write H'00 to TCNT.
(2) In subactive mode, clear the TME bit to 0.
Internal Reset in Watchdog Timer Mode
Switching between Watchdog Timer Mode and Interval Timer Mode
OVF Flag Clearing in Interval Timer Mode
Changing Value of PSS or CKS2 to CKS0
Notes on Initializing TCNT by Using the TME Bit
Rev. 6.00 Mar. 18, 2010 Page 479 of 982
Section 13 Watchdog Timer (WDT)
REJ09B0054-0600