HD64F2239TF20I Renesas Electronics America, HD64F2239TF20I Datasheet - Page 45

• Manufacturer Part Number: HD64F2239TF20I
• Description: MCU 3V 384K I-TEMP 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2200r

Specifications of HD64F2239TF20I

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 72
• Program Memory Size: 384KB (384K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

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Figure 8.39
Section 9 Data Transfer Controller (DTC)
Figure 9.1
Figure 9.2
Figure 9.3
Figure 9.4
Figure 9.5
Figure 9.6
Figure 9.7
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Figure 9.11
Operation in Block Transfer Mode (BLKDIR = 1)..............................................253
Operation Flow in Block Transfer Mode .............................................................254
Example of Block Transfer Mode Setting Procedure...........................................255
Example of DMA Transfer Bus Timing...............................................................256
Example of Short Address Mode Transfer...........................................................257
Example of Full Address Mode Transfer (Cycle Steal) .......................................258
Example of Full Address Mode Transfer (Burst Mode).......................................259
Example of Full Address Mode Transfer (Block Transfer Mode) .......................260
Example of DREQ Pin Falling Edge Activated Normal Mode Transfer .............261
Example of DREQ Pin Falling Edge Activated Block Transfer Mode Transfer..262
Example of DREQ Pin Low Level Activated Normal Mode Transfer.................263
Example of DREQ Pin Low Level Activated Block Transfer Mode Transfer.....264
Example of Single Address Mode Transfer (Byte Read) .....................................265
Example of Single Address Mode (Word Read) Transfer....................................266
Example of Single Address Mode Transfer (Byte Write) ....................................267
Example of Single Address Mode Transfer (Word Write)...................................268
Example of DREQ Pin Falling Edge Activated Single Address Mode Transfer .269
Example of DREQ Pin Low Level Activated Single Address Mode Transfer.....270
Example of Multi-Channel Transfer ....................................................................272
Example of Procedure for Continuing Transfer on Channel Interrupted by NMI
Interrupt................................................................................................................273
Example of Procedure for Forcibly Terminating DMAC Operation....................274
Example of Procedure for Clearing Full Address Mode ......................................274
Block Diagram of Transfer End/Transfer Break Interrupt ...................................275
DMAC Register Update Timing ..........................................................................276
Contention between DMAC Register Update and CPU Read..............................277
Block Diagram of DTC ........................................................................................282
Block Diagram of DTC Activation Source Control .............................................289
The Location of the DTC Register Information in the Address Space.................290
Correspondence between DTC Vector Address and Register Information ..........290
Flowchart of DTC Operation ...............................................................................293
Memory Mapping in Normal Mode .....................................................................294
Memory Mapping in Repeat Mode ......................................................................295
Memory Mapping in Block Transfer Mode .........................................................296
Chain Transfer Operation.....................................................................................297
DTC Operation Timing (Example in Normal Mode or Repeat Mode) ................298
DTC Operation Timing (Example of Block Transfer Mode, with Block
Size of 2) ..............................................................................................................299
Rev. 6.00 Mar. 18, 2010 Page xliii of lx
REJ09B0054-0600