HD64F2239TF20I Renesas Electronics America, HD64F2239TF20I Datasheet - Page 553

• Manufacturer Part Number: HD64F2239TF20I
• Description: MCU 3V 384K I-TEMP 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2200r

Specifications of HD64F2239TF20I

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 72
• Program Memory Size: 384KB (384K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

(7) Parity Bit
The parity bit is used to confirm that transfer data has no error.
The parity bit is added to respective data of the master address, slave address, control, message
length, and data bits.
The even parity is used. When the number of one bits in data is odd, the parity bit is 1. When the
number of one bits in data is even, the parity bit is 0.
(8) Acknowledge Bit
In normal communications (a single unit to a single unit communications), the acknowledge bit is
added to the following position in order to confirm that data is correctly accepted.
• At the end of the slave address field
• At the end of the control field
• At the end of the message length field
• At the end of the data field
The acknowledge bit is defined below.
• 0: indicates that the transfer data is acknowledged. (ACK)
• 1: indicates that the transfer data is not acknowledged. (NAK)
Note that the acknowledge bit is ignored in the case of broadcast communications.
(a) Acknowledge bit at the End of the Slave Address Field
(b) Acknowledge bit at the End of the Control Field
acknowledgement. The master unit reads in the subsequent data if the number of data does not
exceed the maximum number of transfer bytes in one frame.
The acknowledge bit at the end of the slave address field becomes NAK in the following cases
and transfer is stopped.
⎯ When the parity of the master address or slave address bits is incorrect
⎯ When a timing error (an error in bit format) occurs
⎯ When there is no slave unit
The acknowledge bit at the end of the control field becomes NAK in the following cases and
transfer is stopped.
⎯ When the parity of the control bits is incorrect
Section 14 IEBus™ Controller (IEB) [H8S/2258 Group]
Rev. 6.00 Mar. 18, 2010 Page 491 of 982
REJ09B0054-0600