HD64F2239TF20I Renesas Electronics America, HD64F2239TF20I Datasheet - Page 334

• Manufacturer Part Number: HD64F2239TF20I
• Description: MCU 3V 384K I-TEMP 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2200r

Specifications of HD64F2239TF20I

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 72
• Program Memory Size: 384KB (384K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Section 8 DMA Controller (DMAC)
8.5.12
The DMA read cycle and write cycle are inseparable, and so the external bus release cycle and
DTC cycle do not arise between the DMA external read cycle and internal write cycle.
When the read cycle and write cycle are set in series as in a burst transfer or block transfer, the
external bus release may be inserted after the write cycle. As the DTC has a lower priority than the
DMAC, it is not executed until the DMAC releases the bus.
When the DMA read cycle or write cycle accesses the on-chip memory or an internal I/O register,
the DMAC cycle or external bus release may be executed at the same time.
8.5.13
When an NMI interrupt is requested, burst mode transfer in full address mode is interrupted. An
NMI interrupt does not affect the operation of the DMAC in other modes.
In full address mode, transfer is enabled for a channel when both the DTE bit and DTME bit are
set to 1. With burst mode setting, the DTME bit is cleared when an NMI interrupt is requested.
Rev. 6.00 Mar. 18, 2010 Page 272 of 982
REJ09B0054-0600
Address bus
DMA control
Channel 0A
Channel 0B
Channel 1
HWR
LWR
Relation between DMAC and External Bus Requests, and DTC
RD
DMAC and NMI Interrupts
φ
release
Idle
Bus
Request clear
Read
DMA read
Request
hold
Request
hold
Figure 8.33 Example of Multi-Channel Transfer
Write
Channel 0A
transfer
Selection
DMA write
selection
Non-
Idle
release
Request clear
Bus
Read
DMA read
Request
hold
Write
Channel 0B
transfer
Selection
DMA write
Idle
release
Request clear
Bus
Read
DMA read
Channel 1 transfer
Write
DMA write
Read
DMA
read