HD64F2239TF20I Renesas Electronics America, HD64F2239TF20I Datasheet - Page 224

• Manufacturer Part Number: HD64F2239TF20I
• Description: MCU 3V 384K I-TEMP 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2200r

Specifications of HD64F2239TF20I

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 72
• Program Memory Size: 384KB (384K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Section 6 PC Break Controller (PBC)
• When the SLEEP instruction causes a transition to software standby mode or watch mode:
6.3.5
While the break interrupt enable bit is set to 1, instruction execution is one state later than usual.
• For 1-word branch instructions (Bcc d:8, BSR, JSR, JMP, TRAPA, RTE, and RTS) in on-chip
• When break interruption by instruction fetch is set, the set address indicates on-chip ROM or
• When break interruption by instruction fetch is set and a break interrupt is generated, if the
• When break interruption by instruction fetch is set and a break interrupt is generated, if the
Rev. 6.00 Mar. 18, 2010 Page 162 of 982
REJ09B0054-0600
Execution of instruction
after sleep instruction
PC break exception
SLEEP instruction
After execution of the SLEEP instruction, a transition is made to the respective mode, and PC
break interrupt handling is not executed. However, the CMFA or CMFB flag is set (figure 6.2
(D).
ROM or RAM.
RAM space, and that address is used for data access, the instruction that executes the data
access is one state later than in normal operation.
executing instruction immediately preceding the set instruction has one of the addressing
modes shown below, and that address indicates on-chip ROM or RAM, the instruction will be
one state later than in normal operation.
Addressing modes: @ERn, @(d:16,ERn), @(d:32,ERn), @-ERn/ERn+, @aa:8, @aa:24,
@aa:32, @(d:8,PC), @(d:16,PC), @@aa:8
executing instruction immediately preceding the set instruction is NOP or SLEEP, or has #xx,
execution
handling
(A)
When Instruction Execution Is Delayed by One State
Figure 6.2 Operation in Power-Down Mode Transitions
Execution of instruction
after sleep instruction
PC break exception
exception handling
SLEEP instruction
Direct transition
System clock
→ subclock
execution
handling
(B)
Subactive
mode
Execution of instruction
oscillation settling time
after sleep instruction
PC break exception
exception handling
SLEEP instruction
Direct transition
system clock,
Subclock →
execution
handling
(C)
High-speed
(medium-speed)
mode
SLEEP instruction
respective mode
Transition to
execution
(D)