HD64F2239TF20I Renesas Electronics America, HD64F2239TF20I Datasheet - Page 801

• Manufacturer Part Number: HD64F2239TF20I
• Description: MCU 3V 384K I-TEMP 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2200r

Specifications of HD64F2239TF20I

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 72
• Program Memory Size: 384KB (384K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Note: 6. Write Pulse Width
Note: Use a 10 μs write pulse for additional programming.
Number of Writes n
Write pulse application subroutine
1000
Wait t
998
999
Notes: 1. Data transfer is performed by byte transfer. The lower 8 bits of the first address written to must be H'00 or H'80.
Clear PSU1 bit in FLMCR1
10
11
12
13
1
2
3
4
5
6
7
8
9
Reprogram data storage
Additional-programming
Set PSU1 bit in FLMCR1
Sub-Routine Write Pulse
Reprogram Data Computation Table
Clear P1 bit in FLMCR1
Program data storage
Set P1 bit in FLMCR1
data storage area
Original Data
area (128 bytes)
area (128 bytes)
Wait (t
Wait (t
sp10 or
(128 bytes)
Wait (t
2. Verify data is read in 16-bit (word) units.
3. Reprogram data is determined by the operation shown in the table below (comparison between the data stored in the program data area and the verify data). Bits for
4. A 128-byte area for storing program data, a 128-byte area for storing reprogram data, and a 128-byte area for storing additional data must be provided in RAM.
5. A write pulse of 30 μs or 200 μs is applied according to the progress of the programming operation. See Note *6 for details of the pulse widths. When writing of
WDT enable
Disable WDT
(D)
RAM
End Sub
0
0
1
1
A 128-byte data transfer must be performed even if writing fewer than 128 bytes; in this case, H'FF data must be written to the extra addresses.
which the reprogram data is 0 are programmed in the next reprogramming loop. Therefore, even bits for which programming has been completed will be subjected to
programming once again if the result of the subsequent verify operation is NG.
The contents of the reprogram data area and additional data area are modified as programming proceeds.
additional-programming data is executed, a 10 μs write pulse should be applied. Reprogram data X' means reprogram data when the write pulse is applied.
spsu
cpsu
t
cp
sp30 or
) 5 μs
(tsp30/tsp200) μs
) 50 μs
) 5 μs
Figure 20.11 Program/Program-Verify Flowchart
Write Time
Verify Data
200
200
200
200
200
200
200
200
200
200
t
30
30
30
30
30
30
sp200
(V)
0
1
0
1
Reprogram Data
Start of programming
End of programming
*
5
(X)
Increment address
1
0
1
1
Programming completed
Programming incomplete;
reprogram
Still in erased state; no action
Successively write 128-byte data from additional-
programming data area in RAM to flash memory
Apply Write Pulse (Additional programming) 10 μs
No
Comments
Transfer reprogram data to reprogram data area
Additional-programming data computation
Transfer additional-programming data to
Store 128-byte program data in program
data area consecutively to flash memory
Write 128-byte data in RAM reprogram
Apply Write pulse t
H'FF dummy write to verify address
data area and reprogram data area
additional-programming data area
Clear SWE1 bit in FLMCR1
Set SWE1 bit in FLMCR1
Clear PV1 bit in FLMCR1
Reprogram data computation
data verification completed?
Set PV1 bit in FLMCR1
Start of programming
Wait (t
End of programming
Wait (t
Wait (t
Wait (t
Wait (t
Read verify data
Yes
Yes
Write data =
verify data?
Yes
START
128-byte
m = 0 ?
cswe
m = 0
6
6
n = 1
sswe
spvr
spv
≥
cpv
≥
Additional-Programming Data Computation Table
Reprogram Data
n ?
n?
) 100 μs
Yes
Yes
sp
) 4 μs
) 2 μs
Section 20 Flash Memory (F-ZTAT Version)
) 2 μs
) 1 μs
Sub-Routine-Call
Sub-Routine-Call
30 or t
(X')
0
0
1
1
Rev. 6.00 Mar. 18, 2010 Page 739 of 982
sp
200
No
No
No
Verify Data
*
No
*
(V)
See Note 6 for pulse width
2
0
1
0
1
3
*
*
*
4
1
4
*
*
m = 1
4
1
Perform programming in the erased state.
Do not perform additional programming
on previously programmed addresses.
Clear SWE1 bit in FLMCR1
Programming Data (Y)
Wait (t
Programming failure
Additional-
n ≥ 1000?
cswe
0
1
1
1
) 100 μs
Yes
Additional programming
to be executed
Additional programming
not to be executed
Additional programming
not to be executed
Additional programming
not to be executed
No
n ← n + 1
REJ09B0054-0600
Comments
Reprogram