HD64F2239TF20I Renesas Electronics America, HD64F2239TF20I Datasheet - Page 669

• Manufacturer Part Number: HD64F2239TF20I
• Description: MCU 3V 384K I-TEMP 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2200r

Specifications of HD64F2239TF20I

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 72
• Program Memory Size: 384KB (384K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

[3]
No
No
Read receive data in RDR, and
clear RDRF flag in SSR to 0
Clear ORER flag in SSR to 0
Read ORER flag in SSR
Read RDRF flag in SSR
Clear RE bit in SCR to 0
Overrun error processing
All data received?
Figure 15.22 Sample Serial Reception Flowchart
Error processing
Start reception
Initialization
ORER = 1
RDRF = 1
<End>
<End>
Yes
Yes
No
(Continued below)
Error processing
Yes
Section 15 Serial Communication Interface (SCI)
[2]
[1]
[3]
[4]
[5]
Rev. 6.00 Mar. 18, 2010 Page 607 of 982
Notes: 1. Supported only by the H8S/2239
[1] SCI initialization:
[2] [3] Receive error processing:
[4] SCI status check and receive data
[5] Serial reception continuation
The RxD pin is automatically
designated as the receive data input
pin.
If a receive error occurs, read the
ORER flag in SSR, and after
performing the appropriate error
processing, clear the ORER flag to 0.
Transfer cannot be resumed if the
ORER flag is set to 1.
read:
Read SSR and check that the RDRF
flag is set to 1, then read the receive
data in RDR and clear the RDRF flag
to 0.
Transition of the RDRF flag from 0 to 1
can also be identified by an RXI
interrupt.
procedure:
To continue serial reception, before
the final bit of the current frame is
received, reading the RDRF flag,
reading RDR, and clearing the RDRF
flag to 0 should be finished. The
RDRF flag is cleared automatically
when the DMAC *
activated by a receive data full
interrupt (RXI) request and the RDR
value is read.
2. The case, in which the DTC
Group.
automatically clears the RDRF
flag, occurs only when DISEL in
DTC is 0 with the transfer
counter not being 0. Therefore,
the RDRF flag should be
cleared by CPU when DISEL is
1, or when DISEL is 0 with the
transfer counter being 0.
1
or the DTC *
REJ09B0054-0600
2
is