HD64F2239TF20I Renesas Electronics America, HD64F2239TF20I Datasheet - Page 44

• Manufacturer Part Number: HD64F2239TF20I
• Description: MCU 3V 384K I-TEMP 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2200r

Specifications of HD64F2239TF20I

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 72
• Program Memory Size: 384KB (384K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

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Section 8 DMA Controller (DMAC)
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Rev. 6.00 Mar. 18, 2010 Page xlii of lx
REJ09B0054-0600
Overview of Area Divisions................................................................................. 175
CSn Signal Output Timing (n = 0 to 7) ................................................................ 178
On-5Chip Memory Access Cycle ........................................................................ 179
Pin States during On-Chip Memory Access......................................................... 179
On-Chip Peripheral Module Access Cycle .......................................................... 180
Pin States during On-Chip Peripheral Module Access......................................... 180
Access Sizes and Data Alignment Control (8-Bit Access Space) ........................ 181
Access Sizes and Data Alignment Control (16-Bit Access Space) ...................... 182
Bus Timing for 8-Bit 2-State Access Space ......................................................... 183
Bus Timing for 8-Bit 3-State Access Space ......................................................... 184
Bus Timing for 16-Bit 2-State Access Space (1) (Even Address Byte Access)... 185
Bus Timing for 16-Bit 2-State Access Space (2) (Odd Address Byte Access) .... 186
Bus Timing for 16-Bit 2-State Access Space (3) (Word Access) ........................ 187
Bus Timing for 16-Bit 3-State Access Space (1) (Even Address Byte Access)... 188
Bus Timing for 16-Bit 3-State Access Space (2) (Odd Address Byte Access) .... 189
Bus Timing for 16-Bit 3-State Access Space (3) (Word Access) ........................ 190
Example of Wait State Insertion Timing.............................................................. 191
Example of Burst ROM Access Timing (When AST0 = BRSTS1 = 1) .............. 193
Example of Burst ROM Access Timing (When AST0 = BRSTS1 = 0) .............. 193
Example of Idle Cycle Operation (1) ................................................................... 194
Example of Idle Cycle Operation (2) ................................................................... 195
Relationship between Chip Select (CS) and Read (RD) ...................................... 196
Bus-Released State Transition Timing................................................................. 198
Block Diagram of DMAC.................................................................................... 204
Areas for Register Re-Setting by DTC (Channel 0A).......................................... 230
Operation in Sequential Mode.............................................................................. 237
Example of Sequential Mode Setting Procedure.................................................. 238
Operation in Idle Mode ........................................................................................ 239
Example of Idle Mode Setting Procedure ............................................................ 240
Operation in Repeat mode.................................................................................... 242
Example of Repeat Mode Setting Procedure ....................................................... 243
Data Bus in Single Address Mode ....................................................................... 244
Operation in Single Address Mode (when Sequential Mode Is Specified) .......... 246
Example of Single Address Mode Setting Procedure
(when Sequential Mode Is Specified) .................................................................. 247
Operation in Normal Mode .................................................................................. 249
Example of Normal Mode Setting Procedure ...................................................... 250
Operation in Block Transfer Mode (BLKDIR = 0).............................................. 252