HD64F2239TF20I Renesas Electronics America, HD64F2239TF20I Datasheet - Page 357

• Manufacturer Part Number: HD64F2239TF20I
• Description: MCU 3V 384K I-TEMP 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2200r

Specifications of HD64F2239TF20I

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 72
• Program Memory Size: 384KB (384K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Table 9.4 lists the register information in repeat mode. Figure 9.7 shows the memory mapping in
repeat mode.
Table 9.4
Name
DTC source address register
DTC destination address register
DTC transfer count register AH
DTC transfer count register AL
DTC transfer count register B
9.5.3
In block transfer mode, one operation transfers one block of data. Either the transfer source or the
transfer destination is designated as a block area.
The block size can be between 1 to 256. When the transfer of one block ends, the initial state of
the block size counter and the address register specified as the block area is restored. The other
address register is then incremented, decremented, or left fixed.
From 1 to 65,536 transfers can be specified. Once the specified number of transfers have been
completed, a CPU interrupt is requested.
SAR
or
DAR
Block Transfer Mode
Register Information in Repeat Mode
Figure 9.7 Memory Mapping in Repeat Mode
Repeat area
Abbreviation
SAR
DAR
CRAH
CRAL
CRB
Transfer
Rev. 6.00 Mar. 18, 2010 Page 295 of 982
Section 9 Data Transfer Controller (DTC)
Function
Designates source address
Designates destination address
Holds number of transfers
Designates transfer count
Not used
REJ09B0054-0600
DAR
or
SAR