HD64F2239TF20I Renesas Electronics America, HD64F2239TF20I Datasheet - Page 758

• Manufacturer Part Number: HD64F2239TF20I
• Description: MCU 3V 384K I-TEMP 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2200r

Specifications of HD64F2239TF20I

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 72
• Program Memory Size: 384KB (384K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Section 17 A/D Converter
17.4
ADDRA to ADDRD are 16-bit registers. As the data bus to the bus master is 8 bits wide, the bus
master accesses to the upper byte of the registers directly while to the lower byte of the registers
via the temporary register (TEMP).
Data in ADDR is read in the following way: When the upper-byte data is read, the upper-byte data
will be transferred to the CPU and the lower-byte data will be transferred to TEMP. Then, when
the lower-byte data is read, the lower-byte data will be transferred to the CPU.
When data in ADDR is read, the data should be read from the upper byte and lower byte in the
order. When only the upper-byte data is read, the data is guaranteed. However, when only the
lower-byte data is read, the data is not guaranteed.
Figure 17.2 shows data flow when accessing to ADDR.
Rev. 6.00 Mar. 18, 2010 Page 696 of 982
REJ09B0054-0600
Interface to Bus Master
Bus master
Bus master
(H'AA)
(H'40)
Read the upper byte
Read the lower byte
Figure 17.2 Access to ADDR (When Reading H'AA40)
Bus interface
Bus interface
ADDRnH
ADDRnH
(H'AA)
(H'AA)
Module data bus
ADDRnL
Module data bus
ADDRnL
TEMP
(H'40)
(H'40)
TEMP
(H'40)
(H'40)
(n = A to D)
(n = A to D)