HD64F2239TF20I Renesas Electronics America, HD64F2239TF20I Datasheet - Page 569

MCU 3V 384K I-TEMP 100-TQFP

HD64F2239TF20I

Manufacturer Part Number
HD64F2239TF20I
Description
MCU 3V 384K I-TEMP 100-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2200r
Datasheet

Specifications of HD64F2239TF20I

Core Processor
H8S/2000
Core Size
16-Bit
Speed
20MHz
Connectivity
I²C, SCI, SmartCard
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
72
Program Memory Size
384KB (384K x 8)
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
HD64F2239TF20I
Manufacturer:
Renesas Electronics America
Quantity:
10 000
14.3.9
IETBR is a 1-byte buffer to which data to be transmitted in master or slave transmission is written.
IETBR is empty when the TxRDY flag in IETSR is 1. Check the TxRDY flag before setting
transmit data in IETBR.
Data written in IETBR is transmitted in the data field in master or slave transmission. Figure 14.6
shows the correspondence between the communications signal format and registers for IEBus data
transfer.
Bit
7
6
5
4
3
2
1
0
[In master transmission]
Communications frame
Register
[In slave transmission]
Communications frame
Register
Bit Name
TBR7
TBR6
TBR5
TBR4
TBR3
TBR2
TBR1
TBR0
IEBus Transmit Buffer Register (IETBR)
Figure 14.6 Transmission Signal Format and Registers in Data Transfer
Notes: 1. In slave transmission, the received master address is not saved. If the unit is locked,
Initial Value
0
0
0
0
0
0
0
0
Master address
Master address
IEAR1, IEAR2
2. The received slave address is compared with IEAR1 and IEAR2, and if these addresses
3. In slave transmission, the received control bits are not saved. The received control bits
address comparison performed.
match, operation continues.
are decoded to decide the subsequent operation.
(*1)
IEAR1, IEAR2
Slave address
Slave address
IESA1, IESA2
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Section 14 IEBus™ Controller (IEB) [H8S/2258 Group]
(*2)
Description
Data to be transmitted is written to this 1-byte
buffer.
CTL3 to CTL0
Control bits
Control bits
in IEMCR
(*3)
Rev. 6.00 Mar. 18, 2010 Page 507 of 982
Message length
Message length
IETBFL
IETBFL
bits
bits
Data bits
Data bits
IETBR
IETBR
REJ09B0054-0600

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