HD64F2239TF20I Renesas Electronics America, HD64F2239TF20I Datasheet - Page 672

• Manufacturer Part Number: HD64F2239TF20I
• Description: MCU 3V 384K I-TEMP 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2200r

Specifications of HD64F2239TF20I

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 72
• Program Memory Size: 384KB (384K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Section 15 Serial Communication Interface (SCI)
15.7
The SCI supports an IC card (Smart Card) interface that conforms to ISO/IEC 7816-3
(Identification Card) as a serial communication interface extension function. Switching between
the normal serial communication interface and the Smart Card interface mode is carried out by
means of a register setting.
15.7.1
Figure 15.24 shows an example of connection with the Smart Card. In communication with an IC
card, as both transmission and reception are carried out on a single data transmission line, the TxD
pin and RxD pin should be connected to the LSI pin. The data transmission line should be pulled
up to the V
are both set to 1, closed transmission/reception is possible, enabling self-diagnosis to be carried
out. When the clock generated on the Smart Card interface is used by an IC card, the SCK pin
output is input to the CLK pin of the IC card. This LSI port output is used as the reset signal.
15.7.2
Figure 15.25 shows the transfer data format in Smart Card interface mode.
• One frame consists of 8-bit data plus a parity bit in asynchronous mode.
• In transmission, a guard time of at least 2 etu (Elementary Time Unit: the time for transfer of 1
• If a parity error is detected during reception, a low error signal level is output for one etu
• If an error signal is sampled during transmission, the same data is retransmitted automatically
Rev. 6.00 Mar. 18, 2010 Page 610 of 982
REJ09B0054-0600
bit) is left between the end of the parity bit and the start of the next frame.
period, 10.5 etu after the start bit.
after a delay of 2 etu or longer.
Operation in Smart Card Interface
Figure 15.24 Schematic Diagram of Smart Card Interface Pin Connections
Pin Connection Example
Data Format (Except for Block Transfer Mode)
CC
power supply with a resistor. If an IC card is not connected, and the TE and RE bits
Connected equipment
This LSI
Px (port)
SCK
RxD
TxD
Data line
Clock line
Reset line
V
CC
I/O
CLK
RST
IC card