HD64F2239TF20I Renesas Electronics America, HD64F2239TF20I Datasheet - Page 651

• Manufacturer Part Number: HD64F2239TF20I
• Description: MCU 3V 384K I-TEMP 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2200r

Specifications of HD64F2239TF20I

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 72
• Program Memory Size: 384KB (384K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

15.4.4
Before transmitting and receiving data, you should first clear the TE and RE bits in SCR to 0, then
initialize the SCI as described in figure 15.8. When the operating mode, or transfer format, is
changed for example, the TE and RE bits must be cleared to 0 before making the change using the
following procedure. When the TE bit is cleared to 0, the TDRE flag is set to 1. Note that clearing
the RE bit to 0 does not initialize the contents of the RDRF, PER, FER, and ORER flags, or the
contents of RDR. When the external clock is used in asynchronous mode, the clock must be
supplied even during initialization.
Notes: 1. Perform this set operation with the RxD pin in the 1 state. If the RE bit is set to 1 with the RxD pin
SCI Initialization (Asynchronous Mode)
SCR to 1, and set RIE, TIE, TEIE,
Clear TE and RE bits in SCR to 0
Set CKE1 and CKE0 bits in SCR
2. Supported only by the H8S/2239 Group.
Set data transfer format in
<Initialization completion>
in the 0 state, it may be misinterpreted as a start bit.
Set TE and RE
1-bit interval elapsed?
Start initialization
Set value in BRR
SMR and SCMR
(TE, RE bits 0)
and MPIE bits
Figure 15.8 Sample SCI Initialization Flowchart
Yes
*1
bits in
Wait
No
[1]
[2]
[3]
[4]
Section 15 Serial Communication Interface (SCI)
[1] Set the clock selection in SCR.
[2] Set the data transfer format in SMR
[3] Write a value corresponding to the
[4] Wait at least one bit interval, then
Rev. 6.00 Mar. 18, 2010 Page 589 of 982
Be sure to clear bits RIE, TIE,
TEIE, MPIE, TE, and RE, to 0.
When the clock is selected in
asynchronous mode, it is output
immediately after SCR settings are
made.
and SCMR.
bit rate to BRR. Not necessary if
an external clock or an average
transfer rate clock by bits ACS2 to
ACS0 in SEMR_0
set the TE bit or RE bit in SCR to 1.
Also set the RIE, TIE, TEIE, and
MPIE bits.
Setting the TE and RE bits enables
the TxD and RxD pins to be used.
*2
is used.
REJ09B0054-0600