HD64F2239TF20I Renesas Electronics America, HD64F2239TF20I Datasheet - Page 47

• Manufacturer Part Number: HD64F2239TF20I
• Description: MCU 3V 384K I-TEMP 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2200r

Specifications of HD64F2239TF20I

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 72
• Program Memory Size: 384KB (384K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Figure 11.34 Input Capture Input Signal Timing ......................................................................428
Figure 11.35 Counter Clear Timing (Compare Match) .............................................................428
Figure 11.36 Counter Clear Timing (Input Capture) .................................................................429
Figure 11.37 Buffer Operation Timing (Compare Match) ........................................................429
Figure 11.38 Buffer Operation Timing (Input Capture) ............................................................430
Figure 11.39 TGI Interrupt Timing (Compare Match) ..............................................................430
Figure 11.40 TGI Interrupt Timing (Input Capture)..................................................................431
Figure 11.41 TCIV Interrupt Setting Timing.............................................................................431
Figure 11.42 TCIU Interrupt Setting Timing.............................................................................432
Figure 11.43 Timing for Status Flag Clearing by CPU .............................................................432
Figure 11.44 Timing for Status Flag Clearing by DTC/DMAC Activation ..............................433
Figure 11.45 Phase Difference, Overlap, and Pulse Width in Phase Counting Mode ...............434
Figure 11.46 Contention between TCNT Write and Clear Operations......................................435
Figure 11.47 Contention between TCNT Write and Increment Operations ..............................435
Figure 11.48 Contention between TGR Write and Compare Match .........................................436
Figure 11.49 Contention between Buffer Register Write and Compare Match.........................437
Figure 11.50 Contention between TGR Read and Input Capture ..............................................437
Figure 11.51 Contention between TGR Write and Input Capture .............................................438
Figure 11.52 Contention between Buffer Register Write and Input Capture ............................439
Figure 11.53 Contention between Overflow and Counter Clearing ..........................................439
Figure 11.54 Contention between TCNT Write and Overflow .................................................440
Section 12 8-Bit Timers
Figure 12.1
Figure 12.2
Figure 12.3
Figure 12.4
Figure 12.5
Figure 12.6
Figure 12.7
Figure 12.8
Figure 12.9
Figure 12.10 Contention between TCNT Write and Clear ........................................................459
Figure 12.11 Contention between TCNT Write and Increment.................................................460
Figure 12.12 Contention between TCOR Write and Compare-Match ......................................460
Section 13 Watchdog Timer (WDT)
Figure 13.1
Figure 13.1
Figure 13.2
Block Diagram of 8-Bit Timer Module................................................................442
Example of Pulse Output......................................................................................453
Count Timing for Internal Clock Input ................................................................453
Count Timing for External Clock Input ...............................................................454
Timing of CMF Setting ........................................................................................454
Timing of Timer Output.......................................................................................455
Timing of Compare-Match Clear .........................................................................455
Timing of Clearing by External Reset Input ........................................................456
Timing of OVF Setting ........................................................................................456
Block Diagram of WDT_0 (1) .............................................................................466
Block Diagram of WDT_1 (2) .............................................................................467
Watchdog Timer Mode Operation .......................................................................474
Rev. 6.00 Mar. 18, 2010 Page xlv of lx
REJ09B0054-0600