HD64F2239TF20I Renesas Electronics America, HD64F2239TF20I Datasheet - Page 589

• Manufacturer Part Number: HD64F2239TF20I
• Description: MCU 3V 384K I-TEMP 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2200r

Specifications of HD64F2239TF20I

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 72
• Program Memory Size: 384KB (384K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

14.4
14.4.1
This section describes an example of master transmission using the DTC after slave reception.
(1) IEB Initialization
(a) Setting the IEBus Control Register (IECTR)
(b) Setting the IEBus Master Unit Address Registers 1 and 2 (IEAR1 and IEAR2)
(c) Setting the IEBus Slave Address Setting Registers 1 and 2 (IESA1 and IESA2)
(d) Setting the IEBus Master Control register (IEMCR)
(e) Setting the IEBus Transmit Message Length Register (IETBFL)
(f) Setting the IEBus Transmit/Runaway Interrupt Enable Register (IEIET)
The above registers can be specified in any order. (The register specification order does not affect
the IEB operation.)
(2) DTC Initialization
1. Set the start address of the RAM which stores the register information necessary for the DTC
2. Set the following data from the start address of the RAM.
3. Set DTCEG5 in the DTC enable register G (DTCERG) to enable the TxRDY interrupt
Enable the IEBus pins, select the signal polarity, and select a clock supplied to the IEB. Clear
the LUEE bit to 0 since the transfer is performed by the DTC.
Specify the master unit address and specify the communications mode in IEAR1.
Specify the communications destination slave unit address.
Select broadcast/normal communications, specify the number of retransfer counts at arbitration
loss, and specify the control bits.
Specify the message length bits.
Enable TxRDY (IETxI), TxS, TxF, and TxE (IETSI) interrupts.
transfer in the vector address (H'000004D4) to be accessed when a DTC transfer request is
generated.
⎯ Transfer source address (SAR): Start address of the RAM which stores data to be
⎯ Transfer destination address (DAR): Address (H'FFF808) of the IEBus transmit buffer
⎯ Transfer count (CRA): The same value as the IETBFL contents
(IETxI).
transmitted in the data field.
register (IETBR)
Operation Descriptions
Master Transmit Operation
Section 14 IEBus™ Controller (IEB) [H8S/2258 Group]
Rev. 6.00 Mar. 18, 2010 Page 527 of 982
REJ09B0054-0600