HD64F2239TF20I Renesas Electronics America, HD64F2239TF20I Datasheet - Page 114

MCU 3V 384K I-TEMP 100-TQFP

HD64F2239TF20I

Manufacturer Part Number
HD64F2239TF20I
Description
MCU 3V 384K I-TEMP 100-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2200r
Datasheet

Specifications of HD64F2239TF20I

Core Processor
H8S/2000
Core Size
16-Bit
Speed
20MHz
Connectivity
I²C, SCI, SmartCard
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
72
Program Memory Size
384KB (384K x 8)
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
HD64F2239TF20I
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Section 1 Overview
Type
Address bus A23 to
Data bus
Bus
control
Rev. 6.00 Mar. 18, 2010 Page 52 of 982
REJ09B0054-0600
Symbol
A0
D15 to
D0
CS7
CS6
CS5
CS4
CS3
CS2
CS1
CS0
AS
RD
HWR
LWR
WAIT
TFP-100B
TFP-100BV
TFP-100G
TFP-100GV
FP-100B
FP-100BV
37 to 15,
13
100 to 96,
11 to 1
87
88
89
90
92
93
94
95
69
70
71
72
73
FP-100A *
FP-100AV *
40 to 18,
16
100, 99,
14 to 1
90
91
92
93
95
96
97
98
72
73
74
75
76
Pin No.
3
3
BP-112 *
BP-112V *
TBP-112A *
TBP-112AV *
L5, L4, L3,
L2, K5, K4,
K3, K2, K1,
J5, J4, J3,
J2, J1, H5,
H4, H3, H2,
H1, G4, G3,
G2, G1, F1
E4, E3, E1,
D4, D3, D2,
D1, C4, C2,
C1, B4, B3,
B2, B1, A3,
A2
C6
A6
B6
D6
B5
C5
A4
D5
E8
D10
C11
D9
C10
1
1
4
4
I/O
Output
Input/
output
Output
Output
Output
Output
Output
Input
Function
Outputs Address.
Used as the bidirectional data bus.
Select signals for areas 7 to 0.
When this pin is low, it indicates valid
address output on the address bus.
When this pin is low, it indicates that the
external address space is being read.
Strobe signal: Writes to the external
address bus to indicate valid data on the
upper data bus (D15 to D8).
Strobe signal: Writes to the external bus to
indicate valid data on the lower data bus
(D7 to D0).
Requests insertion of wait states in bus
cycle when accesses to the external three-
state address.

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