HD64F2239TF20I Renesas Electronics America, HD64F2239TF20I Datasheet - Page 707

• Manufacturer Part Number: HD64F2239TF20I
• Description: MCU 3V 384K I-TEMP 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2200r

Specifications of HD64F2239TF20I

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 72
• Program Memory Size: 384KB (384K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Bit
3
2
Bit Name
ACKE
BBSY
Initial
Value
0
0
R/W
R/W
R/W
Description
Acknowledge Bit Judgement Selection
0: The value of the acknowledge bit is ignored, and
1: If the acknowledge bit is 1, continuous transfer is
In this LSI, the DTC can be used to perform continuous
transfer. The DTC is activated when the IRTR interrupt flag is
set to 1 (IRTR us one of two interrupt flags, the other being
IRIC). When the ACKE bit is 0, the TDRE, IRIC, and IRTR
flags are set on completion of data transmission, regardless of
the acknowledge bit. When the ACKE bit is 1, the TDRE,
IRIC, and IRTR flags are set on completion of data
transmission when the acknowledge bit is 0, and the IRIC flag
alone is set on completion of data transmission when the
acknowledge bit is 1.
When the DTC is activated, the TDRE, IRIC, and IRTR flags
are cleared to 0 after the specified number of data transfers
have been executed. Consequently, interrupts are not
generated during continuos data transfer, but if data
transmission is completed with a 1 acknowledge bit when the
ACKE bit is set to 1, the DTC is not activated and an interrupt
is generated, if enabled.
Depending on the receiving device, the acknowledge bit may
be significant, in indicating completion of processing of the
received data, for instance, or may be fixed at 1 and have no
significance.
Bus Busy
In slave mode, reading the BBSY flag enables to confirm
whether the I
set to 0 when the SDA level changes from high to low under
the condition of SCl = high, assuming that the start condition
has been issued. The BBSY flag is cleared to 0 when the SDA
level changes from low to high under the condition of SCl =
high, assuming that the start condition has been issued.
Writing to the BBSY flag in slave mode is disabled.
In master mode, the BBSY flag is used to issue start and stop
conditions. Write 1 to BBSY and 0 to SCP to issue a start
condition. Follow this procedure when also re-transmitting a
start condition. To issue a start/stop condition, use the MOV
instruction. The I
transmit mode before the issue of a start condition.
continuous transfer is performed. The value of the received
acknowledge bit is not indicated by the ACKB bit, which is
always 0.
interrupted.
2
C bus is occupied or released. The BBSY flag is
2
C bus interface must be set in master
Section 16 I
Rev. 6.00 Mar. 18, 2010 Page 645 of 982
2
C Bus Interface (IIC) (Option)
REJ09B0054-0600