HD64F2239TF20I Renesas Electronics America, HD64F2239TF20I Datasheet - Page 737
HD64F2239TF20I
Manufacturer Part Number
HD64F2239TF20I
Description
MCU 3V 384K I-TEMP 100-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2200r
Datasheet
1.DF2238RFA6V.pdf
(1048 pages)
Specifications of HD64F2239TF20I
Core Processor
H8S/2000
Core Size
16-Bit
Speed
20MHz
Connectivity
I²C, SCI, SmartCard
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
72
Program Memory Size
384KB (384K x 8)
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Available stocks
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Part Number:
HD64F2239TF20I
Manufacturer:
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10 000
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The following items are not initialized:
• Actual register values (ICDR, SAR, SARX, ICMR, ICCR, ICSR, DDCSWR, and STCR)
• Internal latches used to retain register read information for setting/clearing flags in the ICMR,
• The value of the ICMR register bit counter (BC2 to BC0)
• Generated interrupt sources (interrupt sources transferred to the interrupt controller)
Notes on Initialization:
• Interrupt flags and interrupt sources are not cleared, and so flag clearing measures must be
• Basically, other register flags are not cleared either, and so flag clearing measures must be
• When initialization is performed by means of the DDCSWR register, the write data for bits
• If a flag clearing setting is made during transmission/reception, the IIC module will stop
The value of the BBSY bit cannot be modified directly by this module clear function, but since the
stop condition pin waveform is generated according to the state and release timing of the SCL and
SDA pins, the BBSY bit may be cleared as a result. Similarly, state switching of other bits and
flags may also have an effect.
To prevent problems caused by these factors, the following procedure should be used when
initializing the IIC state.
1. Execute initialization of the internal state according to the setting of bits CLR3 to CLR0, or
2. Execute a stop condition issuance instruction (write 0 to BBSY and SCP) to clear the BBSY
3. Re-execute initialization of the internal state according to the setting of bits CLR3 to CLR0, or
4. Initialize (re-set) the IIC registers.
ICCR, ICSR, and DDCSWR registers
taken as necessary.
taken as necessary.
CLR3 to CLR0 is not retained. To perform IIC clearance, bits CLR3 to CLR0 must be written
to simultaneously using an MOV instruction. Do not use a bit manipulation instruction such as
BCLR. Similarly, when clearing is required again, all the bits must be written to
simultaneously in accordance with the setting.
transmitting/receiving at that point and the SCL and SDA pins will be released. When
transmission/reception is started again, register initialization, etc., must be carried out as
necessary to enable correct communication as a system.
according to the ICE bit.
bit to 0, and wait for two transfer rate clock cycles.
according to the ICE bit.
Section 16 I
Rev. 6.00 Mar. 18, 2010 Page 675 of 982
2
C Bus Interface (IIC) (Option)
REJ09B0054-0600
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