HD64F2239TF20I Renesas Electronics America, HD64F2239TF20I Datasheet - Page 748

• Manufacturer Part Number: HD64F2239TF20I
• Description: MCU 3V 384K I-TEMP 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2200r

Specifications of HD64F2239TF20I

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 72
• Program Memory Size: 384KB (384K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Section 16 I
16. Note on Wait Operation in Master Mode
Rev. 6.00 Mar. 18, 2010 Page 686 of 982
REJ09B0054-0600
(Master transmit mode)
(Master transmit mode)
(Slave receive mode)
Though it is prohibited in the normal I
bit is erroneously set to 1 and a transition to master mode is occurred during data transmission
or reception in slave mode. In multi-master mode, pay attention to the setting of the MST bit
when a bus conflict may occur. In this case, the MST bit in the ICCR register should be set to 1
according to the order below.
(1) Make sure that the BBSY flag in the ICCR register is 0 and the bus is free before setting
(2) Set the MST bit to 1.
(3) To confirm that the bus was not entered to the busy state while the MST bit is being set,
When the interrupt request flag (IRIC) is cleared from 1 to 0 between the falling edge of the
7th clock and the falling edge of the 8th clock in master mode using the wait function, a wait
may not be inserted after the falling edge of the 8th clock and 9th clock pulse may be output
continuously.
When using the wait operation, note the following to clear the IRIC flag.
After the IRIC flag is set to 1 at the rising edge of the 9th clock, clear the IRIC falg before the
rising edge of the 7th clock (when the value of the BC2 to BC0 counter is 2 or more).
If the clearing of the IRIC flag is deleyed due to interrupt handling etc. and the value of the BC
counter reaches 1 or 0, confirm that the SCL pin is low and then clear the IRIC flag after the
BC2 to BC0 counter reaches 0 (see figure 16.28).
I
I
2
2
C bus interface
C bus interface
Other device
the MST bit.
check that the BBSY flag in the ICCR register is 0 immediately after the MST bit has been
set.
Figure 16.27 Diagram of Erroneous Operation Wen Arbitration Is Lost
2
C Bus Interface (IIC) (Option)
S
S
S
• Receive address is ignored
SLA
SLA
SLA
Transmit data match
Transmit timing match
R/W
R/W
R/W
2
C protocol, the same problem may occur when the MST
A
A
A
• Arbitration is lost
• The AL flag in ICSR is set to 1
• Automatically transferred to slave
• Receive data is recognized as an
• When the receive data matches to
receive mode
address
the address set in the SAR or SARX
register, the I
as a slave device.
SLA
DATA1
DATA2
2
C bus interface operates
Transmit data does not match
R/W
A
A
DATA3
DATA4
Data contention
A
A